)]}'
{
  "commit": "32d05420a28fe54bb6f74ef0fa3fd5247be0c2bd",
  "tree": "bf803b34794a5bd077bfb13342765503fc7f5e29",
  "parents": [
    "b6dd152556ce2581f06758efc45c9b387bc4c4ab"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Oct 19 19:43:52 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Oct 19 19:43:52 2020 -0400"
  },
  "message": "Added two additional features:  (1) Timer chaining, which allows one\ntimer to be clocked from the output of the other, forming a 64-bit\ntimer, and (2) User power-good signal, memory-mapped so that the state\nof the user\u0027s 1.8V power domain can be assessed (should have the same\nfor the 3.3V domains).  Also:  The routing of the PLL output and trap\nand IRQ inputs was moved from the single gpio pin to additional bits\nin the user space, and an additional output routing was made for the\nsecondary clock.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "96630f1993a19c56a331dc81a9d1099c5ddda3d2",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/defs.h",
      "new_id": "abfcd44f3b6c87420de014c175e7c59487697ffb",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/defs.h"
    },
    {
      "type": "modify",
      "old_id": "b4fc6a5234803cd97e35f081c53771755dd210d1",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v",
      "new_id": "0086016432b7affa98c792bb309b62c4027657b3",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v"
    },
    {
      "type": "modify",
      "old_id": "e5af073976cff38b3eeda096cc75572873c55344",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "fbaaa5c49ce93706c61d46f0268df682a533bd42",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "9e252819129431e2882184af16c186fda1866dbd",
      "old_mode": 33261,
      "old_path": "verilog/rtl/counter_timer.v",
      "new_id": "f5691824feb4594314d736413f7b695d95c077bf",
      "new_mode": 33261,
      "new_path": "verilog/rtl/counter_timer.v"
    },
    {
      "type": "modify",
      "old_id": "db8d599a0d57f4378ff5375f5e8472c5e38b86fb",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_core.v",
      "new_id": "4e99ee936385f5f69f9d50f5b8ae35b238aa93eb",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_core.v"
    },
    {
      "type": "modify",
      "old_id": "8865ee48e9cd4ea95037c913ae8cf3c04e17b0d7",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_protect.v",
      "new_id": "df32f81c2f254ec54563d6eb2d294e58f70349ac",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_protect.v"
    },
    {
      "type": "modify",
      "old_id": "6778da07cab7448f583f6c2cdde1eccd8118f9ec",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_soc.v",
      "new_id": "6f2173f23dff439ddc1f8506c23531917f9bd97d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_soc.v"
    },
    {
      "type": "modify",
      "old_id": "86ec1e5be02b53ff19087844744a9546d6c59e08",
      "old_mode": 33188,
      "old_path": "verilog/rtl/sysctrl.v",
      "new_id": "acdb04570369c7eede01c7dc5ef2030ea7eb63c6",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sysctrl.v"
    }
  ]
}