diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index b42eedf..fffee90 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -344,8 +344,10 @@
 		.la_output(la_output_core),
 		.la_oen(la_oen),
 		// User Project IO Control
-		.mprj_pwrgood(mprj_pwrgood),
-		.mprj2_pwrgood(mprj2_pwrgood),
+		.mprj_vcc_pwrgood(mprj_vcc_pwrgood),
+		.mprj2_vcc_pwrgood(mprj2_vcc_pwrgood),
+		.mprj_vdd_pwrgood(mprj_vdd_pwrgood),
+		.mprj2_vdd_pwrgood(mprj2_vdd_pwrgood),
 		.mprj_io_loader_resetn(mprj_io_loader_resetn),
 		.mprj_io_loader_clock(mprj_io_loader_clock),
 		.mprj_io_loader_data(mprj_io_loader_data),
@@ -382,14 +384,20 @@
 	wire [3:0]  mprj_sel_o_user;
 	wire [31:0] mprj_adr_o_user;
 	wire [31:0] mprj_dat_o_user;
-	wire	    mprj_pwrgood;
-	wire	    mprj2_pwrgood;
+	wire	    mprj_vcc_pwrgood;
+	wire	    mprj2_vcc_pwrgood;
+	wire	    mprj_vdd_pwrgood;
+	wire	    mprj2_vdd_pwrgood;
 
 	mgmt_protect mgmt_buffers (
 		.vccd(vccd),
 		.vssd(vssd),
 		.vccd1(vccd1),
 		.vssd1(vssd1),
+		.vdda1(vdda1),
+		.vssa1(vssa1),
+		.vdda2(vdda2),
+		.vssa2(vssa2),
 
 		.caravel_clk(caravel_clk),
 		.caravel_clk2(caravel_clk2),
@@ -413,8 +421,10 @@
 		.mprj_adr_o_user(mprj_adr_o_user),
 		.mprj_dat_o_user(mprj_dat_o_user),
 		.la_data_in_mprj(la_data_in_mprj),
-		.user1_powergood(mprj_pwrgood),
-		.user2_powergood(mprj2_pwrgood)
+		.user1_vcc_powergood(mprj_vcc_pwrgood),
+		.user2_vcc_powergood(mprj2_vcc_pwrgood),
+		.user1_vdd_powergood(mprj_vdd_pwrgood),
+		.user2_vdd_powergood(mprj2_vdd_pwrgood)
 	);
 
 	
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index cd8a232..e7511c6 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -45,8 +45,10 @@
 	// User Project Control Signals
 	input [MPRJ_IO_PADS-1:0] mgmt_in_data,
 	output [MPRJ_IO_PADS-1:0] mgmt_out_data,
-	input mprj_pwrgood,
-	input mprj2_pwrgood,
+	input mprj_vcc_pwrgood,
+	input mprj2_vcc_pwrgood,
+	input mprj_vdd_pwrgood,
+	input mprj2_vdd_pwrgood,
 	output mprj_io_loader_resetn,
 	output mprj_io_loader_clock,
 	output mprj_io_loader_data,
@@ -184,8 +186,10 @@
 		.la_output(la_output),
 		.la_oen(la_oen),
 		// User Project I/O Configuration
-		.mprj_pwrgood(mprj_pwrgood),
-		.mprj2_pwrgood(mprj2_pwrgood),
+		.mprj_vcc_pwrgood(mprj_vcc_pwrgood),
+		.mprj2_vcc_pwrgood(mprj2_vcc_pwrgood),
+		.mprj_vdd_pwrgood(mprj_vdd_pwrgood),
+		.mprj2_vdd_pwrgood(mprj2_vdd_pwrgood),
 		.mprj_io_loader_resetn(mprj_io_loader_resetn),
 		.mprj_io_loader_clock(mprj_io_loader_clock),
 		.mprj_io_loader_data(mprj_io_loader_data),
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index df32f81..4dcf111 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -20,6 +20,10 @@
     inout	  vssd1,
     inout	  vccd2,
     inout	  vssd2,
+    inout	  vdda1,
+    inout	  vssa1,
+    inout	  vdda2,
+    inout	  vssa2,
 
     input 	  caravel_clk,
     input 	  caravel_clk2,
@@ -43,14 +47,24 @@
     output [31:0] mprj_adr_o_user,
     output [31:0] mprj_dat_o_user,
     output [127:0] la_data_in_mprj,
-    output	  user1_powergood,
-    output	  user2_powergood
+    output	  user1_vcc_powergood,
+    output	  user2_vcc_powergood,
+    output	  user1_vdd_powergood,
+    output	  user2_vdd_powergood
 );
 
 	wire [74:0] mprj_logic1;
 	wire mprj2_logic1;
-	wire user1_powergood;
-	wire user2_powergood;
+
+	wire mprj_vdd_logic1_h;
+	wire mprj2_vdd_logic1_h;
+	wire mprj_vdd_logic1;
+	wire mprj2_vdd_logic1;
+
+	wire user1_vcc_powergood;
+	wire user2_vcc_powergood;
+	wire user1_vdd_powergood;
+	wire user2_vdd_powergood;
 
         sky130_fd_sc_hd__conb_1 mprj_logic_high [74:0] (
                 .VPWR(vccd1),
@@ -70,6 +84,47 @@
                 .LO()
         );
 
+	// Logic high in the VDDA (3.3V) domains
+
+        sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl (
+                .VPWR(vdda1),
+                .VGND(vssa1),
+                .VPB(vdda1),
+                .VNB(vssa1),
+                .HI(mprj_vdd_logic1_h),
+                .LO()
+        );
+
+        sky130_fd_sc_hvl__conb_1 mprj2_logic_high_hvl (
+                .VPWR(vdda2),
+                .VGND(vssa2),
+                .VPB(vdda2),
+                .VNB(vssa2),
+                .HI(mprj2_vdd_logic1_h),
+                .LO()
+        );
+
+	// Level shift the logic high signals into the 1.8V domain
+
+	sky130_fd_sc_hvl__lsbufhv2lv mprj_logic_high_lv (
+		.VPWR(vdda1),
+		.VGND(vssd),
+		.LVPWR(vccd),
+		.VPB(vdda1),
+		.VNB(vssd),
+		.X(mprj_vdd_logic1),
+		.A(mprj_vdd_logic1_h)
+	);
+
+	sky130_fd_sc_hvl__lsbufhv2lv mprj2_logic_high_lv (
+		.VPWR(vdda2),
+		.VGND(vssd),
+		.LVPWR(vccd),
+		.VPB(vdda2),
+		.VNB(vssd),
+		.X(mprj2_vdd_logic1),
+		.A(mprj2_vdd_logic1_h)
+	);
 
         sky130_fd_sc_hd__einvp_8 mprj_rstn_buf (
                 .VPWR(vccd),
@@ -187,7 +242,7 @@
                 .VPB(vccd),
                 .VNB(vssd),
                 .A(mprj_logic1[74]),
-                .X(user1_powergood)
+                .X(user1_vcc_powergood)
 	);
 
         sky130_fd_sc_hd__buf_8 mprj2_pwrgood (
@@ -195,8 +250,25 @@
                 .VGND(vssd),
                 .VPB(vccd),
                 .VNB(vssd),
-                .A(mprj_logic2),
-                .X(user2_powergood)
+                .A(mprj2_logic1),
+                .X(user2_vcc_powergood)
 	);
 
+        sky130_fd_sc_hd__buf_8 mprj_vdd_pwrgood (
+                .VPWR(vccd),
+                .VGND(vssd),
+                .VPB(vccd),
+                .VNB(vssd),
+                .A(mprj_vdd_logic1),
+                .X(user_vdd_powergood)
+	);
+
+        sky130_fd_sc_hd__buf_8 mprj2_vdd_pwrgood (
+                .VPWR(vccd),
+                .VGND(vssd),
+                .VPB(vccd),
+                .VNB(vssd),
+                .A(mprj2_vdd_logic1),
+                .X(user2_vdd_powergood)
+	);
 endmodule
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 8d7dc71..ac4fdf5 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -70,8 +70,10 @@
     output [127:0] la_oen,              // LA output enable (active low) 
 
     // User Project I/O Configuration (serial load)
-    input  mprj_pwrgood,
-    input  mprj2_pwrgood,
+    input  mprj_vcc_pwrgood,
+    input  mprj2_vcc_pwrgood,
+    input  mprj_vdd_pwrgood,
+    input  mprj2_vdd_pwrgood,
     output mprj_io_loader_resetn,
     output mprj_io_loader_clock,
     output mprj_io_loader_data,
@@ -588,8 +590,10 @@
         .wb_ack_o(sys_ack_o),
         .wb_dat_o(sys_dat_o),
 
-	.usr1_pwrgood(mprj_pwrgood),
-	.usr2_pwrgood(mprj2_pwrgood),
+	.usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+	.usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+	.usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+	.usr2_vdd_pwrgood(mprj2_vdd_pwrgood),
         .trap_output_dest(trap_output_dest),
         .clk1_output_dest(clk1_output_dest),
         .clk2_output_dest(clk2_output_dest),
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index acdb045..6c2d376 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -18,8 +18,10 @@
     output [31:0] wb_dat_o,
     output wb_ack_o,
     
-    input  usr1_pwrgood,
-    input  usr2_pwrgood,
+    input  usr1_vcc_pwrgood,
+    input  usr2_vcc_pwrgood,
+    input  usr1_vdd_pwrgood,
+    input  usr2_vdd_pwrgood,
     output clk1_output_dest,
     output clk2_output_dest,
     output trap_output_dest,
@@ -56,8 +58,10 @@
         .iomem_rdata(wb_dat_o),
         .iomem_ready(ready),
         
-	.usr1_pwrgood(usr1_pwrgood),
-	.usr2_pwrgood(usr2_pwrgood),
+	.usr1_vcc_pwrgood(usr1_vcc_pwrgood),
+	.usr2_vcc_pwrgood(usr2_vcc_pwrgood),
+	.usr1_vdd_pwrgood(usr1_vdd_pwrgood),
+	.usr2_vdd_pwrgood(usr2_vdd_pwrgood),
         .clk1_output_dest(clk1_output_dest),
         .clk2_output_dest(clk2_output_dest),
         .trap_output_dest(trap_output_dest), 
@@ -84,8 +88,10 @@
     output reg [31:0] iomem_rdata,
     output reg iomem_ready,
 
-    input  usr1_pwrgood,
-    input  usr2_pwrgood,
+    input  usr1_vcc_pwrgood,
+    input  usr2_vcc_pwrgood,
+    input  usr1_vdd_pwrgood,
+    input  usr2_vdd_pwrgood,
     output clk1_output_dest,
     output clk2_output_dest,
     output trap_output_dest,
@@ -99,8 +105,10 @@
     reg irq_7_inputsrc;
     reg irq_8_inputsrc;
 
-    wire usr1_pwrgood;
-    wire usr2_pwrgood;
+    wire usr1_vcc_pwrgood;
+    wire usr2_vcc_pwrgood;
+    wire usr1_vdd_pwrgood;
+    wire usr2_vdd_pwrgood;
 
     assign pwrgood_sel  = (iomem_addr[7:0] == PWRGOOD);
     assign clk_out_sel  = (iomem_addr[7:0] == CLK_OUT);
@@ -120,7 +128,8 @@
                 iomem_ready <= 1'b 1;
                 
                 if (pwrgood_sel) begin
-                    iomem_rdata <= {30'd0, usr2_pwrgood, usr1_pwrgood};
+                    iomem_rdata <= {28'd0, usr2_vdd_pwrgood, usr1_vdd_pwrgood,
+				usr2_vcc_pwrgood, usr1_vcc_pwrgood};
 		    // These are read-only bits;  no write behavior on wstrb.
 
                 end else if (clk_out_sel) begin