| ,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/accelerator_top,accelerator_top,17-12_22-02,0h22m11s,1.9362419999999998,18295.75022130498,76232.29258877075,-1,1729.84,35425,0,0,0,0,0,0,0,7,0,-1,1823552,318761,-29.45,-46.89,-12.46,-41.06,-11.7,-52975.62,-86074.46,-20721.58,-59945.61,-594.14,1308202067,0.0,19.49,21.62,0.37,0.04,-1,35204,35792,4319,4907,0,0,0,35425,536,140,708,1694,3161,4495,2874,12021,2677,3852,80,1010,24587,0,25597,31.545741324921135,31.7,20,2,6,24,1,153.6,153.18,0.28,0,sky130_fd_sc_hd,4,0 |
