,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
0,/project/openlane/accelerator_top,accelerator_top,17-12_01-11,0h15m41s,1.5951440000000001,17471.14994006811,72796.45808361712,-1,1673.96,27869,0,0,0,0,0,0,0,5,0,-1,2125292,285417,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1835226751,0.0,27.91,28.14,3.53,0.13,-1,27648,28236,3118,3706,0,0,0,27869,309,130,260,819,1209,3538,2127,9247,3200,3136,38,916,20238,0,21154,50.0,20.0,20,2,6,24,1,153.6,153.18,0.28,0,sky130_fd_sc_hd,4,0