Rebase design (including separate submodule) onto mpw-one-b
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..4907b9b
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "crypto-accelerator-chip"]
+ path = crypto-accelerator-chip
+ url = https://github.com/asinghani/crypto-accelerator-chip.git
diff --git a/compress.py b/compress.py
new file mode 100644
index 0000000..34faca8
--- /dev/null
+++ b/compress.py
@@ -0,0 +1,38 @@
+import os
+import subprocess
+
+FIND_CMD = "find . -type f -size +99M"
+EXCLUDE = [".git"]
+
+proc = subprocess.Popen(FIND_CMD, shell=True, stdout=subprocess.PIPE)
+proc.wait()
+files = [x.decode().strip() for x in proc.stdout.readlines() if len(x.strip()) > 10]
+
+print("Found large files:")
+print("\n".join(files))
+
+basedir = os.getcwd()
+
+for file in files:
+ if any([x in file for x in EXCLUDE]):
+ print("Skipping {}...".format(file))
+ continue
+
+ inp = ""
+ while len(inp.strip()) < 1:
+ inp = input("Compress file {} [y/n]? ".format(file))
+
+ if inp != "y":
+ print("Skipping {}...".format(file))
+ continue
+
+ dirname, filename = os.path.split(file)
+ print("Entering {}".format(dirname, filename))
+ os.chdir(dirname)
+
+ subprocess.Popen("ls -1 | grep {}".format(filename), shell=True).wait()
+ os.system("gzip {}".format(filename))
+ subprocess.Popen("ls -1 | grep {}".format(filename), shell=True).wait()
+
+ os.chdir(basedir)
+ print("Done compressing {}".format(filename))
diff --git a/crypto-accelerator-chip b/crypto-accelerator-chip
new file mode 160000
index 0000000..86deb9c
--- /dev/null
+++ b/crypto-accelerator-chip
@@ -0,0 +1 @@
+Subproject commit 86deb9c8c638195998f13d638b58726b27e3f125
diff --git a/migrate-gl.sh b/migrate-gl.sh
new file mode 100755
index 0000000..eceb2de
--- /dev/null
+++ b/migrate-gl.sh
@@ -0,0 +1,7 @@
+if [ "$1" == "" ] || [ $# -gt 1 ]; then
+ echo "Usage: $0 <path to accelerator_top run>"
+ exit 0
+fi
+
+cp openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis.v verilog/gl/user_project_wrapper.v
+cp $1/results/synthesis/accelerator_top.synthesis.v verilog/gl/accelerator_top.v
diff --git a/openlane/accelerator_top/config.tcl b/openlane/accelerator_top/config.tcl
new file mode 120000
index 0000000..d1c0f0d
--- /dev/null
+++ b/openlane/accelerator_top/config.tcl
@@ -0,0 +1 @@
+../../crypto-accelerator-chip/openlane/accelerator_top/config.tcl
\ No newline at end of file
diff --git a/openlane/accelerator_top/interactive.tcl b/openlane/accelerator_top/interactive.tcl
new file mode 120000
index 0000000..b894ca2
--- /dev/null
+++ b/openlane/accelerator_top/interactive.tcl
@@ -0,0 +1 @@
+../../crypto-accelerator-chip/openlane/accelerator_top/interactive.tcl
\ No newline at end of file
diff --git a/openlane/accelerator_top/pin_order.cfg b/openlane/accelerator_top/pin_order.cfg
new file mode 120000
index 0000000..f0b71ff
--- /dev/null
+++ b/openlane/accelerator_top/pin_order.cfg
@@ -0,0 +1 @@
+../../crypto-accelerator-chip/openlane/accelerator_top/pin_order.cfg
\ No newline at end of file
diff --git a/openlane/accelerator_top/scripts b/openlane/accelerator_top/scripts
new file mode 120000
index 0000000..10443dd
--- /dev/null
+++ b/openlane/accelerator_top/scripts
@@ -0,0 +1 @@
+../../crypto-accelerator-chip/openlane/accelerator_top/scripts/
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
new file mode 120000
index 0000000..e8a4e0f
--- /dev/null
+++ b/openlane/user_project_wrapper/config.tcl
@@ -0,0 +1 @@
+../../crypto-accelerator-chip/openlane/user_project_wrapper/config.tcl
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/gen_pdn.tcl b/openlane/user_project_wrapper/gen_pdn.tcl
new file mode 120000
index 0000000..a1c4306
--- /dev/null
+++ b/openlane/user_project_wrapper/gen_pdn.tcl
@@ -0,0 +1 @@
+../../crypto-accelerator-chip/openlane/user_project_wrapper/gen_pdn.tcl
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
new file mode 120000
index 0000000..a6a943f
--- /dev/null
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -0,0 +1 @@
+../../crypto-accelerator-chip/openlane/user_project_wrapper/interactive.tcl
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
new file mode 120000
index 0000000..2caf44c
--- /dev/null
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -0,0 +1 @@
+../../crypto-accelerator-chip/openlane/user_project_wrapper/macro.cfg
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/pdn.tcl b/openlane/user_project_wrapper/pdn.tcl
new file mode 120000
index 0000000..f7226ee
--- /dev/null
+++ b/openlane/user_project_wrapper/pdn.tcl
@@ -0,0 +1 @@
+../../crypto-accelerator-chip/openlane/user_project_wrapper/pdn.tcl
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
new file mode 120000
index 0000000..9a44cc7
--- /dev/null
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -0,0 +1 @@
+../../crypto-accelerator-chip/openlane/user_project_wrapper/pin_order.cfg
\ No newline at end of file
diff --git a/update-verilog.sh b/update-verilog.sh
new file mode 100755
index 0000000..ced4eec
--- /dev/null
+++ b/update-verilog.sh
@@ -0,0 +1,18 @@
+#!/bin/sh
+# Copyright 2020 Anish Singhani
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+cd crypto-accelerator-chip && sh ./update-verilog.sh && cd ..
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
deleted file mode 100644
index 49cd280..0000000
--- a/verilog/dv/README.md
+++ /dev/null
@@ -1,30 +0,0 @@
-<!---
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
--->
-# DV Tests
-
-Organized into two subdirectories:
- * caravel: contains tests for both the mangement SoC and an example user project.
- * wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus
-
-<pre>
-├── caravel
-│ ├── mgmt_soc
-│ ├── user_proj_example
-└── wb_utests
-</pre>
-
diff --git a/verilog/dv/caravel/accelerator b/verilog/dv/caravel/accelerator
new file mode 120000
index 0000000..43e0bbf
--- /dev/null
+++ b/verilog/dv/caravel/accelerator
@@ -0,0 +1 @@
+../../../crypto-accelerator-chip/verilog/dv/caravel/accelerator/
\ No newline at end of file
diff --git a/verilog/rtl/accelerator b/verilog/rtl/accelerator
new file mode 120000
index 0000000..fa4b43d
--- /dev/null
+++ b/verilog/rtl/accelerator
@@ -0,0 +1 @@
+../../crypto-accelerator-chip/verilog/rtl/accelerator
\ No newline at end of file
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
new file mode 120000
index 0000000..685d5a6
--- /dev/null
+++ b/verilog/rtl/user_project_wrapper.v
@@ -0,0 +1 @@
+../../crypto-accelerator-chip/verilog/rtl/user_project_wrapper.v
\ No newline at end of file
