)]}'
{
  "commit": "2340904d5e8f7e62b480ecd075b945f24ef0d843",
  "tree": "2dabfa8f165c88e5c15e16b0286f5dc10a720b52",
  "parents": [
    "45a6942481fbc45715961c661d3b928d189d6e74"
  ],
  "author": {
    "name": "Anish",
    "email": "anish_oss@anishsinghani.com",
    "time": "Wed Dec 16 13:00:56 2020 -0800"
  },
  "committer": {
    "name": "Anish",
    "email": "anish_oss@anishsinghani.com",
    "time": "Wed Dec 16 13:00:56 2020 -0800"
  },
  "message": "Test mangling GPIO test\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "73dd397e1d83cb0ee929da07332a9de768dde112",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio.c",
      "new_id": "ae6e621e6362c33bd5117264431bdc718df03f46",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "94da39dcf30f7893b685123b7652475c03abd425",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/printio.h"
    }
  ]
}