diff --git a/verilog/dv/dummy_slave.v b/verilog/dv/dummy_slave.v
new file mode 100644
index 0000000..857ce0e
--- /dev/null
+++ b/verilog/dv/dummy_slave.v
@@ -0,0 +1,33 @@
+module dummy_slave(
+    input wb_clk_i,
+    input wb_rst_i,
+    
+    input wb_stb_i,
+    input wb_cyc_i,
+    input wb_we_i,
+    input [3:0] wb_sel_i,
+    input [31:0] wb_adr_i,
+    input [31:0] wb_dat_i,
+    
+    output reg [31:0] wb_dat_o,
+    output reg wb_ack_o
+);
+    reg [31:0] store;
+
+    wire valid = wb_cyc_i & wb_stb_i;
+
+    always @(posedge wb_clk_i) begin
+        if (wb_rst_i == 1'b 1) begin
+            wb_ack_o <= 1'b 0;
+        end else begin
+            if (wb_we_i == 1'b 1) begin
+                if (wb_sel_i[0]) store[7:0]   <= wb_dat_i[7:0];
+                if (wb_sel_i[1]) store[15:8]  <= wb_dat_i[15:8];
+                if (wb_sel_i[2]) store[23:16] <= wb_dat_i[23:16];
+                if (wb_sel_i[3]) store[31:24] <= wb_dat_i[31:24];
+            end
+            wb_dat_o <= store;
+            wb_ack_o <= valid & !wb_ack_o;
+        end
+    end
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/harness/mgmt_soc/Makefile b/verilog/dv/harness/mgmt_soc/Makefile
new file mode 100644
index 0000000..c934af3
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/Makefile
@@ -0,0 +1,18 @@
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = gpio mem uart perf hkspi sysctrl xbar
+
+all:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+	done
+
+clean:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make clean ) ; \
+	done
+
+.PHONY: clean all
diff --git a/verilog/dv/harness/mgmt_soc/defs.h b/verilog/dv/harness/mgmt_soc/defs.h
new file mode 100644
index 0000000..e2d777f
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/defs.h
@@ -0,0 +1,96 @@
+#ifndef _STRIVE_H_
+#define _STRIVE_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// a pointer to this is a null pointer, but the compiler does not
+// know that because "sram" is a linker symbol from sections.lds.
+extern uint32_t sram;
+
+// Pointer to firmware flash routines
+extern uint32_t flashio_worker_begin;
+extern uint32_t flashio_worker_end;
+
+// IOs: UART (0x2000_0000), GPIO (0x2100_0000), LA (0x2200_0000)
+#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_uart_data   (*(volatile uint32_t*)0x20000004)
+
+#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
+#define reg_gpio_ena  (*(volatile uint32_t*)0x21000004)
+#define reg_gpio_pu   (*(volatile uint32_t*)0x21000008)
+#define reg_gpio_pd   (*(volatile uint32_t*)0x2100000c)
+
+#define reg_la0_data (*(volatile uint32_t*)0x22000000)
+#define reg_la1_data (*(volatile uint32_t*)0x22000004)
+#define reg_la2_data (*(volatile uint32_t*)0x22000008)
+#define reg_la3_data (*(volatile uint32_t*)0x2200000c)
+
+#define reg_la0_ena (*(volatile uint32_t*)0x22000010)
+#define reg_la1_ena (*(volatile uint32_t*)0x22000014)
+#define reg_la2_ena (*(volatile uint32_t*)0x22000018)
+#define reg_la3_ena (*(volatile uint32_t*)0x2200001c)
+
+// Flash Control SPI Configuration (2D00_0000)
+#define reg_spictrl (*(volatile uint32_t*)0x2D000000)         
+
+// House-Keeping SPI Read-Only Registers (0x2E00_0000)
+#define reg_spi_config     (*(volatile uint32_t*)0x2E000000)
+#define reg_spi_enables    (*(volatile uint32_t*)0x2E000004)
+#define reg_spi_pll_config (*(volatile uint32_t*)0x2E000008)
+#define reg_spi_mfgr_id    (*(volatile uint32_t*)0x2E00000c)
+#define reg_spi_prod_id    (*(volatile uint32_t*)0x2E000010)
+#define reg_spi_mask_rev   (*(volatile uint32_t*)0x2E000014)
+#define reg_spi_pll_bypass (*(volatile uint32_t*)0x2E000018)
+
+// System Area (0x2F00_0000)
+#define reg_rcosc_enable   (*(volatile uint32_t*)0x2F000000)
+#define reg_rcosc_out_dest (*(volatile uint32_t*)0x2F000004)
+
+#define reg_xtal_out_dest (*(volatile uint32_t*)0x2F000008)
+#define reg_pll_out_dest  (*(volatile uint32_t*)0x2F00000c)
+#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000010)
+
+#define reg_irq7_source (*(volatile uint32_t*)0x2F000014)
+#define reg_irq8_source (*(volatile uint32_t*)0x2F000018)
+
+#define reg_overtemp_ena      (*(volatile uint32_t*)0x2F00001c)
+#define reg_overtemp_data     (*(volatile uint32_t*)0x2F000020)
+#define reg_overtemp_out_dest (*(volatile uint32_t*)0x2F000024)
+
+// Crosbbar Slave Addresses (0x8000_0000 - 0xB000_0000)
+#define qspi_ctrl_slave    (*(volatile uint32_t*)0x80000000)
+#define storage_area_slave (*(volatile uint32_t*)0x90000000)
+#define mega_any_slave1    (*(volatile uint32_t*)0xA0000000)
+#define mega_any_slave2    (*(volatile uint32_t*)0xB0000000)
+
+// #define reg_adc0_ena (*(volatile uint32_t*)0x21000010)
+// #define reg_adc0_data (*(volatile uint32_t*)0x21000014)
+// #define reg_adc0_done (*(volatile uint32_t*)0x21000018)
+// #define reg_adc0_convert (*(volatile uint32_t*)0x2100001c)
+// #define reg_adc0_clk_source (*(volatile uint32_t*)0x21000020)
+// #define reg_adc0_input_source (*(volatile uint32_t*)0x21000024)
+
+// #define reg_adc1_ena (*(volatile uint32_t*)0x21000030)
+// #define reg_adc1_data (*(volatile uint32_t*)0x21000034)
+// #define reg_adc1_done (*(volatile uint32_t*)0x21000038)
+// #define reg_adc1_convert (*(volatile uint32_t*)0x2100003c)
+// #define reg_adc1_clk_source (*(volatile uint32_t*)0x21000040)
+// #define reg_adc1_input_source (*(volatile uint32_t*)0x21000044)
+
+// #define reg_dac_ena (*(volatile uint32_t*)0x21000050)
+// #define reg_dac_data (*(volatile uint32_t*)0x21000054)
+
+// #define reg_comp_enable (*(volatile uint32_t*)0x21000060)
+// #define reg_comp_n_source (*(volatile uint32_t*)0x21000064)
+// #define reg_comp_p_source (*(volatile uint32_t*)0x21000068)
+// #define reg_comp_out_dest (*(volatile uint32_t*)0x2100006c)
+
+// #define reg_analog_out_sel (*(volatile uint32_t*)0x210000c0)
+// #define reg_analog_out_bias_ena (*(volatile uint32_t*)0x210000c4)
+// #define reg_analog_out_ena (*(volatile uint32_t*)0x210000c8)
+
+// #define reg_bandgap_ena (*(volatile uint32_t*)0x210000d0)
+
+// --------------------------------------------------------
+#endif
diff --git a/verilog/dv/harness/mgmt_soc/gpio/Makefile b/verilog/dv/harness/mgmt_soc/gpio/Makefile
new file mode 100644
index 0000000..e9253c0
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/gpio/Makefile
@@ -0,0 +1,33 @@
+.SUFFIXES:
+
+PATTERN = gpio
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c ../sections.lds ../start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+
+%.hex: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/harness/mgmt_soc/gpio/gpio.c b/verilog/dv/harness/mgmt_soc/gpio/gpio.c
new file mode 100644
index 0000000..17a4885
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/gpio/gpio.c
@@ -0,0 +1,39 @@
+#include "../defs.h"
+
+// --------------------------------------------------------
+
+/*
+	GPIO Test
+		Tests PU and PD on the lower 8 pins while being driven from outside
+		Tests Writing to the upper 8 pins
+		Tests reading from the lower 8 pins
+*/
+void main()
+{
+	int i;
+
+	/* Lower 8 pins are input and upper 8 pins are o/p */
+	reg_gpio_data = 0;
+	reg_gpio_ena =  0x00ff;
+
+	// change the pull up and pull down (checked by the TB)
+	reg_gpio_data = 0xA000;
+	reg_gpio_pu = 0x000f;
+	reg_gpio_pd = 0x00f0;
+
+	reg_gpio_data = 0x0B00;
+	reg_gpio_pu = 0x00f0;
+	reg_gpio_pd = 0x000f;
+
+	reg_gpio_pu = 0x000f;
+	reg_gpio_pd = 0x00f0;
+
+	// read the lower 8 pins, add 1 then o/p the result
+	// checked by the TB
+	reg_gpio_data = 0xAB00;
+	while (1){
+		int x = reg_gpio_data & 0xff;
+		reg_gpio_data = (x+1) << 8;
+	}
+}
+
diff --git a/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v
new file mode 100644
index 0000000..c20ba26
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v
@@ -0,0 +1,194 @@
+/*
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "harness.v"
+`include "spiflash.v"
+
+module gpio_tb;
+	reg XCLK;
+
+	wire VDD3V3;
+	assign VDD3V3 = 1'b1;
+
+	reg XI;
+
+	reg real adc_h, adc_l;
+	reg real adc_0, adc_1;
+	reg real comp_n, comp_p;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #10 XCLK <= (XCLK === 1'b0);
+	always #220 XI <= (XI === 1'b0);
+
+	initial begin
+		XI = 0;
+		XCLK = 0;
+	end
+
+	initial begin
+		// Analog input pin values
+		adc_h = 0.0;
+		adc_l = 0.0;
+		adc_0 = 0.0;
+		adc_1 = 0.0;
+		comp_n = 0.0;
+		comp_p = 0.0;
+		#2000;
+		adc_h = 3.25;
+		adc_l = 0.05;
+		adc_0 = 1.0;
+		adc_1 = 1.5;
+		comp_n = 2.0;
+		comp_p = 2.5;
+	end
+
+	initial begin
+		$dumpfile("gpio.vcd");
+		$dumpvars(0, gpio_tb);
+
+		// Repeat cycles of 1000 XCLK edges as needed to complete testbench
+		repeat (25) begin
+			repeat (1000) @(posedge XCLK);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+		 $display("%c[0m",27);
+		$finish;
+	end
+
+	wire [15:0] gpio;
+
+	reg [7:0] gpio_lo;
+	wire [7:0] gpio_hi;
+
+	assign gpio[7:0] = gpio_lo;
+	assign gpio_hi = gpio[15:8];
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+
+	reg SDI, CSB, SCK, RSTB;
+	wire SDO;
+
+	// Transactor
+	initial begin
+		gpio_lo = {8{1'bz}};
+		wait(gpio_hi==8'hA0);
+		gpio_lo = 8'hF0;
+		wait(gpio_hi==8'h0B);
+		gpio_lo = 8'h0F;
+		wait(gpio_hi==8'hAB);
+		gpio_lo = 8'h0;
+		repeat (1000) @(posedge XCLK);
+		gpio_lo = 8'h1;
+		repeat (1000) @(posedge XCLK);
+		gpio_lo = 8'h3;
+	end
+
+	// Monitor
+	initial begin
+		wait(gpio_hi==8'hA0);
+		wait(gpio[7:0]==8'hF0);
+		wait(gpio_hi==8'h0B);
+		wait(gpio[7:0]==8'h0F);
+		wait(gpio_hi==8'hAB);
+		wait(gpio[7:0]==8'h00);
+		wait(gpio_hi==8'h01);
+		wait(gpio[7:0]==8'h01);
+		wait(gpio_hi==8'h02);
+		wait(gpio[7:0]==8'h03);
+		wait(gpio_hi==8'h04);
+		$display("Monitor: Test GPIO (RTL) Passed");
+		$finish;
+	end
+
+	initial begin
+		CSB <= 1'b1;
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		RSTB <= 1'b0;
+		
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+		CSB <= 1'b0;	    // Apply CSB to start transmission
+	end
+
+	always @(gpio) begin
+		#1 $display("GPIO state = %b (%d - %d)", gpio, gpio_hi, gpio_lo);
+	end
+
+	wire VDD1V8;
+	wire VSS;
+
+	assign VSS = 1'b0;
+	assign VDD1V8 = 1'b1;
+
+	harness uut (
+		.vdd	  (VDD3V3),
+		.vdd1v8	  (VDD1V8),
+		.vss	  (VSS),
+		.xi	  	  (XI),
+		.xclk	  (XCLK),
+		.SDI	  (SDI),
+		.SDO	  (SDO),
+		.CSB	  (CSB),
+		.SCK	  (SCK),
+		.ser_rx	  (1'b0),
+		.ser_tx	  (),
+		.irq	  (1'b0),
+		.gpio     (gpio),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.flash_io2(flash_io2),
+		.flash_io3(flash_io3),
+		.adc_high (adc_h),
+		.adc_low  (adc_l),
+		.adc0_in  (adc_0),
+		.adc1_in  (adc_1),
+		.RSTB	  (RSTB),
+		.comp_inp (comp_p),
+		.comp_inn (comp_n)
+	);
+
+	spiflash #(
+		.FILENAME("gpio.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(flash_io2),
+		.io3(flash_io3)
+	);
+
+endmodule
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/Makefile b/verilog/dv/harness/mgmt_soc/hkspi/Makefile
new file mode 100644
index 0000000..2850baa
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/hkspi/Makefile
@@ -0,0 +1,31 @@
+.SUFFIXES:
+
+PATTERN = hkspi
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c ../sections.lds ../start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+
+%.hex: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< /dev/stdout | sed -e '1 s/@10000000/@00000000/; 2,65537 d;' > $@
+
+%.bin: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c b/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c
new file mode 100644
index 0000000..d572727
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c
@@ -0,0 +1,38 @@
+#include "../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+	if (c == '\n')
+		putchar('\r');
+	reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+	while (*p)
+		putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+	// Set clock to 64 kbaud
+	reg_uart_clkdiv = 625;
+
+	// NOTE: Crystal is running in simulation at 5MHz
+	// Internal clock is 8x crystal, or 40MHz
+	// Divided by clkdiv is 64 kHz
+	// So at this crystal rate, use clkdiv = 4167 for 9600 baud.
+
+	// This should appear at the output, received by the testbench UART.
+        print("\n");
+        print("  ____  _          ____         ____\n");
+        print(" |  _ \\(_) ___ ___/ ___|  ___  / ___|\n");
+        print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n");
+        print(" |  __/| | (_| (_) |__) | (_) | |___\n");
+        print(" |_|   |_|\\___\\___/____/ \\___/ \\____|\n");
+}
+
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v
new file mode 100644
index 0000000..0edc43d
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v
@@ -0,0 +1,256 @@
+/*	
+	StriVe housekeeping SPI testbench.
+*/
+
+`timescale 1 ns / 1 ps
+
+`include "harness.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module hkspi_tb;
+	reg XCLK;
+	reg XI;
+
+	reg real adc_h, adc_l;
+	reg real adc_0, adc_1;
+	reg real comp_n, comp_p;
+	reg SDI, CSB, SCK, RSTB;
+
+
+	wire [15:0] gpio;
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+
+	wire SDO;
+
+	always #10 XCLK <= (XCLK === 1'b0);
+	always #220 XI <=  (XI === 1'b0);
+
+	initial begin
+		XI = 0;
+		XCLK = 0;
+	end
+
+	initial begin
+		// Analog input pin values (static)
+		adc_h = 0.0;
+		adc_l = 0.0;
+		adc_0 = 0.0;
+		adc_1 = 0.0;
+		comp_n = 0.0;
+		comp_p = 0.0;
+	end
+
+    // The main testbench is here.  Put the housekeeping SPI into
+    // pass-thru mode and read several bytes from the flash SPI.
+
+    // First define tasks for SPI functions
+
+	task start_csb;
+	    begin
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		CSB <= 1'b0;
+		#50;
+	    end
+	endtask
+
+	task end_csb;
+	    begin
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		CSB <= 1'b1;
+		#50;
+	    end
+	endtask
+
+	task write_byte;
+	    input [7:0] odata;
+	    begin
+		SCK <= 1'b0;
+		for (i=7; i >= 0; i--) begin
+		    #50;
+		    SDI <= odata[i];
+                    #50;
+		    SCK <= 1'b1;
+                    #100;
+		    SCK <= 1'b0;
+		end
+	    end
+	endtask
+
+	task read_byte;
+	    output [7:0] idata;
+	    begin
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		for (i=7; i >= 0; i--) begin
+		    #50;
+                    idata[i] = SDO;
+                    #50;
+		    SCK <= 1'b1;
+                    #100;
+		    SCK <= 1'b0;
+		end
+	    end
+	endtask
+
+	task read_write_byte
+	    (input [7:0] odata,
+	    output [7:0] idata);
+	    begin
+		SCK <= 1'b0;
+		for (i=7; i >= 0; i--) begin
+		    #50;
+		    SDI <= odata[i];
+                    idata[i] = SDO;
+                    #50;
+		    SCK <= 1'b1;
+                    #100;
+		    SCK <= 1'b0;
+		end
+	    end
+	endtask
+	
+	integer i;
+
+    // Now drive the digital signals on the housekeeping SPI
+	reg [7:0] tbdata;
+
+	initial begin
+	    $dumpfile("hkspi.vcd");
+	    $dumpvars(0, hkspi_tb);
+
+	    CSB <= 1'b1;
+	    SCK <= 1'b0;
+	    SDI <= 1'b0;
+	    RSTB <= 1'b0;
+
+	    // Delay, then bring chip out of reset
+	    #1000;
+	    RSTB <= 1'b1;
+	    #2000;
+
+        // First do a normal read from the housekeeping SPI to
+	    // make sure the housekeeping SPI works.
+
+		start_csb();
+		write_byte(8'h40);	// Read stream command
+		write_byte(8'h03);	// Address (register 3 = product ID)
+	    read_byte(tbdata);
+	    end_csb();
+	    #10;
+	    $display("Read data = 0x%02x (should be 0x05)", tbdata);
+
+	    // Toggle external reset
+		start_csb();
+		write_byte(8'h80);	// Write stream command
+		write_byte(8'h07);	// Address (register 7 = external reset)
+		write_byte(8'h01);	// Data = 0x01 (apply external reset)
+		end_csb();
+
+		start_csb();
+		write_byte(8'h80);	// Write stream command
+		write_byte(8'h07);	// Address (register 7 = external reset)
+		write_byte(8'h00);	// Data = 0x00 (release external reset)
+		end_csb();
+
+	    // Read all registers (0 to 8)
+		start_csb();
+		write_byte(8'h40);	// Read stream command
+		write_byte(8'h00);	// Address (register 3 = product ID)
+	    read_byte(tbdata);
+	    $display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
+		if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+	    read_byte(tbdata);
+	    $display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
+		if(tbdata != 8'h14) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+	    read_byte(tbdata);
+	    $display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
+		if(tbdata != 8'h56) begin $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; end
+	    read_byte(tbdata);
+	    $display("Read register 3 = 0x%02x (should be 0x05)", tbdata);
+		if(tbdata != 8'h05) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+	    read_byte(tbdata);
+	    $display("Read register 4 = 0x%02x (should be 0x07)", tbdata);
+		if(tbdata != 8'h07) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+	    read_byte(tbdata);
+	    $display("Read register 5 = 0x%02x (should be 0x01)", tbdata);
+		if(tbdata != 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+	    read_byte(tbdata);
+	    $display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
+		if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+	    read_byte(tbdata);
+	    $display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
+		if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+	    read_byte(tbdata);
+	    $display("Read register 8 = 0x%02x (should be 0x00)", tbdata);
+		if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		
+        end_csb();
+
+		$display("Monitor: Test HK SPI (RTL) Passed");
+
+	    #10000;
+ 	    $finish;
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = 1'b1;
+	assign VSS = 1'b0;
+	assign VDD1V8 = 1'b1;
+
+	harness uut (
+		.vdd	  (VDD3V3),
+		.vdd1v8	  (VDD1V8),
+		.vss	  (VSS),
+		.xi	      (XI),
+		.xclk	  (XCLK),
+		.SDI	  (SDI),
+		.SDO	  (SDO),
+		.CSB	  (CSB),
+		.SCK	  (SCK),
+		.ser_rx	  (1'b0),
+		.ser_tx	  (tbuart_rx),
+		.irq	  (1'b0),
+		.gpio     (gpio),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.flash_io2(flash_io2),
+		.flash_io3(flash_io3),
+		.adc_high (adc_h),
+		.adc_low  (adc_l),
+		.adc0_in  (adc_0),
+		.adc1_in  (adc_1),
+		.RSTB	  (RSTB),
+		.comp_inp (comp_p),
+		.comp_inn (comp_n)
+	);
+
+	spiflash #(
+		.FILENAME("hkspi.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(flash_io2),
+		.io3(flash_io3)
+	);
+
+	tbuart tbuart (
+		.ser_rx(tbuart_rx)
+	);
+		
+endmodule
diff --git a/verilog/dv/harness/mgmt_soc/mem/Makefile b/verilog/dv/harness/mgmt_soc/mem/Makefile
new file mode 100644
index 0000000..d63df1b
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/mem/Makefile
@@ -0,0 +1,34 @@
+
+.SUFFIXES:
+
+PATTERN = mem
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c ../sections.lds ../start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+
+%.hex: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@                     
+
+%.bin: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/harness/mgmt_soc/mem/mem.c b/verilog/dv/harness/mgmt_soc/mem/mem.c
new file mode 100644
index 0000000..0bff65d
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/mem/mem.c
@@ -0,0 +1,51 @@
+#include "../defs.h"
+
+// --------------------------------------------------------
+
+/*
+	Memory Test
+	It uses GPIO to flag the success or failure of the test
+*/
+unsigned int ints[10];
+unsigned short shorts[10];
+unsigned char bytes[10];
+
+void main()
+{
+	int i;
+
+	/* All GPIO pins are configured to be output */
+	reg_gpio_data = 0;
+	reg_gpio_ena =  0x0000;
+
+	// start test
+	reg_gpio_data = 0xA040;
+
+	// Test Word R/W
+	for(i=0; i<10; i++)
+		ints[i] = i*5000 + 10000;
+	
+	for(i=0; i<10; i++)
+		if((i*5000+10000) != ints[i]) reg_gpio_data = 0xAB40;
+	reg_gpio_data = 0xAB41;
+	
+	// Test Half Word R/W
+	reg_gpio_data = 0xA020;
+	for(i=0; i<10; i++)
+		shorts[i] = i*500 + 100;
+	
+	for(i=0; i<10; i++)
+		if((i*500+100) != shorts[i]) reg_gpio_data = 0xAB20;
+	reg_gpio_data = 0xAB21;
+
+	// Test byte R/W
+	reg_gpio_data = 0xA010;
+	for(i=0; i<10; i++)
+		bytes[i] = i*5 + 10;
+	
+	for(i=0; i<10; i++)
+		if((i*5+10) != bytes[i]) reg_gpio_data = 0xAB10;
+	reg_gpio_data = 0xAB11;
+
+}
+
diff --git a/verilog/dv/harness/mgmt_soc/mem/mem_tb.v b/verilog/dv/harness/mgmt_soc/mem/mem_tb.v
new file mode 100644
index 0000000..09bb0a7
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/mem/mem_tb.v
@@ -0,0 +1,189 @@
+/*
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "harness.v"
+`include "spiflash.v"
+
+module mem_tb;
+	reg XCLK;
+	reg XI;
+
+	reg real adc_h, adc_l;
+	reg real adc_0, adc_1;
+	reg real comp_n, comp_p;
+	reg SDI, CSB, SCK, RSTB;
+
+	wire [15:0] gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+	wire SDO;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #10 XCLK <= (XCLK === 1'b0);
+	always #220 XI <= (XI === 1'b0);
+
+	initial begin
+		XI = 0;
+		XCLK = 0;
+	end
+
+	initial begin
+		// Analog input pin values
+		adc_h = 0.0;
+		adc_l = 0.0;
+		adc_0 = 0.0;
+		adc_1 = 0.0;
+		comp_n = 0.0;
+		comp_p = 0.0;
+		#2000;
+		adc_h = 3.25;
+		adc_l = 0.05;
+		adc_0 = 1.0;
+		adc_1 = 1.5;
+		comp_n = 2.0;
+		comp_p = 2.5;
+	end
+
+	initial begin
+		$dumpfile("mem.vcd");
+		$dumpvars(0, mem_tb);
+
+		// Repeat cycles of 1000 XCLK edges as needed to complete testbench
+		repeat (100) begin
+			repeat (1000) @(posedge XCLK);
+			//$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Timeout, Test MEM (RTL) Failed");
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		CSB <= 1'b1;
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		RSTB <= 1'b0;
+		
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+		CSB <= 1'b0;	    // Apply CSB to start transmission
+	end
+
+	always @(gpio) begin
+		if(gpio == 16'hA040) begin
+			$display("Mem Test (word rw) started");
+		end
+		else if(gpio == 16'hAB40) begin
+			$display("%c[1;31m",27);
+			$display("Monitor: Test MEM (RTL) [word rw] failed");
+			$display("%c[0m",27);
+			$finish;
+		end
+		else if(gpio == 16'hAB41) begin
+			$display("Monitor: Test MEM (RTL) [word rw]  passed");
+		end
+		else if(gpio == 16'hA020) begin
+			$display("Mem Test (short rw) started");
+		end
+		else if(gpio == 16'hAB20) begin
+			$display("%c[1;31m",27);
+			$display("Monitor: Test MEM (RTL) [short rw] failed");
+			$display("%c[0m",27);
+			$finish;
+		end
+		else if(gpio == 16'hAB21) begin
+			$display("Monitor: Test MEM (RTL) [short rw]  passed");
+		end
+		else if(gpio == 16'hA010) begin
+			$display("Mem Test (byte rw) started");
+		end
+		else if(gpio == 16'hAB10) begin
+			$display("%c[1;31m",27);
+			$display("Monitor: Test MEM (RTL) [byte rw] failed");
+			$display("%c[0m",27);
+			$finish;
+		end
+		else if(gpio == 16'hAB11) begin
+			$display("Monitor: Test MEM (RTL) [byte rw] passed");
+			$finish;
+		end
+
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VSS = 1'b0;
+	assign VDD3V3 = 1'b1;
+	assign VDD1V8 = 1'b1;
+
+	harness uut (
+		.vdd	  (VDD3V3),
+		.vdd1v8	  (VDD1V8),
+		.vss	  (VSS),
+		.xi	      (XI),
+		.xclk	  (XCLK),
+		.SDI	  (SDI),
+		.SDO	  (SDO),
+		.CSB	  (CSB),
+		.SCK	  (SCK),
+		.ser_rx	  (1'b0),
+		.ser_tx	  (),
+		.irq	  (1'b0),
+		.gpio     (gpio),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.flash_io2(flash_io2),
+		.flash_io3(flash_io3),
+		.adc_high (adc_h),
+		.adc_low  (adc_l),
+		.adc0_in  (adc_0),
+		.adc1_in  (adc_1),
+		.RSTB	  (RSTB),
+		.comp_inp (comp_p),
+		.comp_inn (comp_n)
+	);
+
+	spiflash #(
+		.FILENAME("mem.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(flash_io2),
+		.io3(flash_io3)
+	);
+
+endmodule
diff --git a/verilog/dv/harness/mgmt_soc/perf/Makefile b/verilog/dv/harness/mgmt_soc/perf/Makefile
new file mode 100644
index 0000000..dad371f
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/perf/Makefile
@@ -0,0 +1,34 @@
+.SUFFIXES:
+
+PATTERN = perf
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	$< -o $@
+	
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c ../sections.lds ../start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+
+%.hex: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/harness/mgmt_soc/perf/perf.c b/verilog/dv/harness/mgmt_soc/perf/perf.c
new file mode 100644
index 0000000..4dc34b1
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/perf/perf.c
@@ -0,0 +1,33 @@
+#include "../defs.h"
+
+// --------------------------------------------------------
+
+/*
+	Performance Test
+	It uses GPIO to flag the success or failure of the test
+*/
+unsigned int ints[50];
+unsigned short shorts[50];
+unsigned char bytes[50];
+
+int main()
+{
+	int i;
+    int sum = 0;
+
+	/* All GPIO pins are configured to be output */
+	reg_gpio_data = 0;
+	reg_gpio_ena =  0x0000;
+
+	// start test
+	reg_gpio_data = 0xA000;
+	
+    for(i=0; i<100; i++)
+        sum+=(sum + i);
+    
+    reg_gpio_data = 0xAB00;
+    
+    return sum;
+	
+}
+
diff --git a/verilog/dv/harness/mgmt_soc/perf/perf_tb.v b/verilog/dv/harness/mgmt_soc/perf/perf_tb.v
new file mode 100644
index 0000000..edd10ba
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/perf/perf_tb.v
@@ -0,0 +1,165 @@
+/*
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "harness.v"
+`include "spiflash.v"
+
+module striVe_perf_tb;
+	reg XCLK;
+	reg XI;
+
+	reg real adc_h, adc_l;
+	reg real adc_0, adc_1;
+	reg real comp_n, comp_p;
+	reg SDI, CSB, SCK, RSTB;
+
+	wire [15:0] gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+	wire SDO;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #10 XCLK <= (XCLK === 1'b0);
+	always #220 XI <= (XI === 1'b0);
+
+	initial begin
+		XI = 0;
+		XCLK = 0;
+	end
+
+	initial begin
+		// Analog input pin values
+		adc_h = 0.0;
+		adc_l = 0.0;
+		adc_0 = 0.0;
+		adc_1 = 0.0;
+		comp_n = 0.0;
+		comp_p = 0.0;
+		#2000;
+		adc_h = 3.25;
+		adc_l = 0.05;
+		adc_0 = 1.0;
+		adc_1 = 1.5;
+		comp_n = 2.0;
+		comp_p = 2.5;
+	end
+
+	reg [31:0] kcycles;
+
+	initial begin
+		$dumpfile("striVe_perf.vcd");
+		$dumpvars(0, striVe_perf_tb);
+
+		kcycles = 0;
+		// Repeat cycles of 1000 XCLK edges as needed to complete testbench
+		repeat (150) begin
+			repeat (1000) @(posedge XCLK);
+			//$display("+1000 cycles");
+			kcycles<=kcycles+1;
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Timeout, Test Performance (RTL) Failed");
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		CSB <= 1'b1;
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		RSTB <= 1'b0;
+		
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+		CSB <= 1'b0;	    // Apply CSB to start transmission
+	end
+
+	always @(gpio) begin
+		//#1 $display("GPIO state = %X ", gpio);
+		if(gpio == 16'hA000) begin
+			kcycles = 0;
+			$display("Performance Test started");
+		end
+		else if(gpio == 16'hAB00) begin
+			//$display("Monitor: number of cycles/100 iterations: %d KCycles", kcycles);
+			$display("Monitor: Test Performance (RTL) passed [%0d KCycles]", kcycles);
+			$finish;
+		end
+	end
+	
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VSS = 1'b0;
+	assign VDD1V8 = 1'b1;
+	assign VDD3V3 = 1'b1;
+
+	harness uut (
+		.vdd	  (VDD3V3  ),
+		.vdd1v8	  (VDD1V8),
+		.vss	  (VSS),
+		.xi	  (XI),
+		.xclk	  (XCLK),
+		.SDI	  (SDI),
+		.SDO	  (SDO),
+		.CSB	  (CSB),
+		.SCK	  (SCK),
+		.ser_rx	  (1'b0),
+		.ser_tx	  (	    ),
+		.irq	  (1'b0	    ),
+		.gpio     (gpio),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.flash_io2(flash_io2),
+		.flash_io3(flash_io3),
+		.adc_high (adc_h),
+		.adc_low  (adc_l),
+		.adc0_in  (adc_0),
+		.adc1_in  (adc_1),
+		.RSTB	  (RSTB),
+		.comp_inp (comp_p),
+		.comp_inn (comp_n)
+	);
+
+	spiflash #(
+		.FILENAME("perf.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(flash_io2),
+		.io3(flash_io3)
+	);
+
+endmodule
diff --git a/verilog/dv/harness/mgmt_soc/sections.lds b/verilog/dv/harness/mgmt_soc/sections.lds
new file mode 100644
index 0000000..4392c6d
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/sections.lds
@@ -0,0 +1,58 @@
+MEMORY {
+	FLASH (rx)	: ORIGIN = 0x10000000, LENGTH = 0x400000 	/* 4MB */
+	RAM(xrw)	: ORIGIN = 0x00000000, LENGTH = 0x400		/* 256 words ( 1024 ? ) */ 
+}
+
+SECTIONS {
+	/* The program code and other data goes into FLASH */
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)	/* .text sections (code) */
+		*(.text*)	/* .text* sections (code) */
+		*(.rodata)	/* .rodata sections (constants, strings, etc.) */
+		*(.rodata*)	/* .rodata* sections (constants, strings, etc.) */
+		*(.srodata)	/* .srodata sections (constants, strings, etc.) */
+		*(.srodata*)	/* .srodata*sections (constants, strings, etc.) */
+		. = ALIGN(4);
+		_etext = .;		/* define a global symbol at end of code */
+		_sidata = _etext;	/* This is used by the startup to initialize data */
+	} >FLASH
+
+	/* Initialized data section */
+	.data : AT ( _sidata )
+	{
+		. = ALIGN(4);
+		_sdata = .;
+		_ram_start = .;
+		. = ALIGN(4);
+		*(.data)
+		*(.data*)
+		*(.sdata)
+		*(.sdata*)
+		. = ALIGN(4);
+		_edata = .;
+	} >RAM
+
+	/* Uninitialized data section */
+	.bss :
+	{
+		. = ALIGN(4);
+		_sbss = .;
+		*(.bss)
+		*(.bss*)
+		*(.sbss)
+		*(.sbss*)
+		*(COMMON)
+
+		. = ALIGN(4);
+		_ebss = .;
+	} >RAM
+
+	/* Define the start of the heap */
+	.heap :
+	{
+		. = ALIGN(4);
+		_heap_start = .;
+	} >RAM
+}
diff --git a/verilog/dv/harness/mgmt_soc/spiflash.v b/verilog/dv/harness/mgmt_soc/spiflash.v
new file mode 100644
index 0000000..0b236e0
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/spiflash.v
@@ -0,0 +1,413 @@
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+//
+// Simple SPI flash simulation model
+//
+// This model samples io input signals 1ns before the SPI clock edge and
+// updates output signals 1ns after the SPI clock edge.
+//
+// Supported commands:
+//    AB, B9, FF, 03, BB, EB, ED
+//
+// Well written SPI flash data sheets:
+//    Cypress S25FL064L http://www.cypress.com/file/316661/download
+//    Cypress S25FL128L http://www.cypress.com/file/316171/download
+//
+
+module spiflash #(
+	parameter FILENAME = "firmware.hex"
+)(
+	input csb,
+	input clk,
+	inout io0, // MOSI
+	inout io1, // MISO
+	inout io2,
+	inout io3
+);
+	localparam verbose = 0;
+	localparam integer latency = 8;
+	
+	reg [7:0] buffer;
+	integer bitcount = 0;
+	integer bytecount = 0;
+	integer dummycount = 0;
+
+	reg [7:0] spi_cmd;
+	reg [7:0] xip_cmd = 0;
+	reg [23:0] spi_addr;
+
+	reg [7:0] spi_in;
+	reg [7:0] spi_out;
+	reg spi_io_vld;
+
+	reg powered_up = 0;
+
+	localparam [3:0] mode_spi         = 1;
+	localparam [3:0] mode_dspi_rd     = 2;
+	localparam [3:0] mode_dspi_wr     = 3;
+	localparam [3:0] mode_qspi_rd     = 4;
+	localparam [3:0] mode_qspi_wr     = 5;
+	localparam [3:0] mode_qspi_ddr_rd = 6;
+	localparam [3:0] mode_qspi_ddr_wr = 7;
+
+	reg [3:0] mode = 0;
+	reg [3:0] next_mode = 0;
+
+	reg io0_oe = 0;
+	reg io1_oe = 0;
+	reg io2_oe = 0;
+	reg io3_oe = 0;
+
+	reg io0_dout = 0;
+	reg io1_dout = 0;
+	reg io2_dout = 0;
+	reg io3_dout = 0;
+
+	assign #1 io0 = io0_oe ? io0_dout : 1'bz;
+	assign #1 io1 = io1_oe ? io1_dout : 1'bz;
+	assign #1 io2 = io2_oe ? io2_dout : 1'bz;
+	assign #1 io3 = io3_oe ? io3_dout : 1'bz;
+
+	wire io0_delayed;
+	wire io1_delayed;
+	wire io2_delayed;
+	wire io3_delayed;
+
+	assign #1 io0_delayed = io0;
+	assign #1 io1_delayed = io1;
+	assign #1 io2_delayed = io2;
+	assign #1 io3_delayed = io3;
+
+	// 16 MB (128Mb) Flash
+	reg [7:0] memory [0:16*1024*1024-1];
+
+	initial begin
+		$display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+			memory[1048576], memory[1048577], memory[1048578],
+			memory[1048579], memory[1048580]);
+		$display("Reading %s",  FILENAME);
+		$readmemh(FILENAME, memory);
+		$display("%s loaded into memory", FILENAME);
+		$display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+			memory[1048576], memory[1048577], memory[1048578],
+			memory[1048579], memory[1048580]);
+	end
+
+	task spi_action;
+		begin
+			spi_in = buffer;
+
+			if (bytecount == 1) begin
+				spi_cmd = buffer;
+
+				if (spi_cmd == 8'h ab)
+					powered_up = 1;
+
+				if (spi_cmd == 8'h b9)
+					powered_up = 0;
+
+				if (spi_cmd == 8'h ff)
+					xip_cmd = 0;
+			end
+
+			if (powered_up && spi_cmd == 'h 03) begin
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount >= 4) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			if (powered_up && spi_cmd == 'h bb) begin
+				if (bytecount == 1)
+					mode = mode_dspi_rd;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount == 5) begin
+					xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+					mode = mode_dspi_wr;
+					dummycount = latency;
+				end
+
+				if (bytecount >= 5) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			if (powered_up && spi_cmd == 'h eb) begin
+				if (bytecount == 1)
+					mode = mode_qspi_rd;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount == 5) begin
+					xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+					mode = mode_qspi_wr;
+					dummycount = latency;
+				end
+
+				if (bytecount >= 5) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			if (powered_up && spi_cmd == 'h ed) begin
+				if (bytecount == 1)
+					next_mode = mode_qspi_ddr_rd;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount == 5) begin
+					xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+					mode = mode_qspi_ddr_wr;
+					dummycount = latency;
+				end
+
+				if (bytecount >= 5) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			spi_out = buffer;
+			spi_io_vld = 1;
+
+			if (verbose) begin
+				if (bytecount == 1)
+					$write("<SPI-START>");
+				$write("<SPI:%02x:%02x>", spi_in, spi_out);
+			end
+
+		end
+	endtask
+
+	task ddr_rd_edge;
+		begin
+			buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed};
+			bitcount = bitcount + 4;
+			if (bitcount == 8) begin
+				bitcount = 0;
+				bytecount = bytecount + 1;
+				spi_action;
+			end
+		end
+	endtask
+
+	task ddr_wr_edge;
+		begin
+			io0_oe = 1;
+			io1_oe = 1;
+			io2_oe = 1;
+			io3_oe = 1;
+
+			io0_dout = buffer[4];
+			io1_dout = buffer[5];
+			io2_dout = buffer[6];
+			io3_dout = buffer[7];
+
+			buffer = {buffer, 4'h 0};
+			bitcount = bitcount + 4;
+			if (bitcount == 8) begin
+				bitcount = 0;
+				bytecount = bytecount + 1;
+				spi_action;
+			end
+		end
+	endtask
+
+	always @(csb) begin
+		if (csb) begin
+			if (verbose) begin
+				$display("");
+				$fflush;
+			end
+			buffer = 0;
+			bitcount = 0;
+			bytecount = 0;
+			mode = mode_spi;
+			io0_oe = 0;
+			io1_oe = 0;
+			io2_oe = 0;
+			io3_oe = 0;
+		end else
+		if (xip_cmd) begin
+			buffer = xip_cmd;
+			bitcount = 0;
+			bytecount = 1;
+			spi_action;
+		end
+	end
+
+	always @(csb, clk) begin
+		spi_io_vld = 0;
+		if (!csb && !clk) begin
+			if (dummycount > 0) begin
+				io0_oe = 0;
+				io1_oe = 0;
+				io2_oe = 0;
+				io3_oe = 0;
+			end else
+			case (mode)
+				mode_spi: begin
+					io0_oe = 0;
+					io1_oe = 1;
+					io2_oe = 0;
+					io3_oe = 0;
+					io1_dout = buffer[7];
+				end
+				mode_dspi_rd: begin
+					io0_oe = 0;
+					io1_oe = 0;
+					io2_oe = 0;
+					io3_oe = 0;
+				end
+				mode_dspi_wr: begin
+					io0_oe = 1;
+					io1_oe = 1;
+					io2_oe = 0;
+					io3_oe = 0;
+					io0_dout = buffer[6];
+					io1_dout = buffer[7];
+				end
+				mode_qspi_rd: begin
+					io0_oe = 0;
+					io1_oe = 0;
+					io2_oe = 0;
+					io3_oe = 0;
+				end
+				mode_qspi_wr: begin
+					io0_oe = 1;
+					io1_oe = 1;
+					io2_oe = 1;
+					io3_oe = 1;
+					io0_dout = buffer[4];
+					io1_dout = buffer[5];
+					io2_dout = buffer[6];
+					io3_dout = buffer[7];
+				end
+				mode_qspi_ddr_rd: begin
+					ddr_rd_edge;
+				end
+				mode_qspi_ddr_wr: begin
+					ddr_wr_edge;
+				end
+			endcase
+			if (next_mode) begin
+				case (next_mode)
+					mode_qspi_ddr_rd: begin
+						io0_oe = 0;
+						io1_oe = 0;
+						io2_oe = 0;
+						io3_oe = 0;
+					end
+					mode_qspi_ddr_wr: begin
+						io0_oe = 1;
+						io1_oe = 1;
+						io2_oe = 1;
+						io3_oe = 1;
+						io0_dout = buffer[4];
+						io1_dout = buffer[5];
+						io2_dout = buffer[6];
+						io3_dout = buffer[7];
+					end
+				endcase
+				mode = next_mode;
+				next_mode = 0;
+			end
+		end
+	end
+
+	always @(posedge clk) begin
+		if (!csb) begin
+			if (dummycount > 0) begin
+				dummycount = dummycount - 1;
+			end else
+			case (mode)
+				mode_spi: begin
+					buffer = {buffer, io0};
+					bitcount = bitcount + 1;
+					if (bitcount == 8) begin
+						bitcount = 0;
+						bytecount = bytecount + 1;
+						spi_action;
+					end
+				end
+				mode_dspi_rd, mode_dspi_wr: begin
+					buffer = {buffer, io1, io0};
+					bitcount = bitcount + 2;
+					if (bitcount == 8) begin
+						bitcount = 0;
+						bytecount = bytecount + 1;
+						spi_action;
+					end
+				end
+				mode_qspi_rd, mode_qspi_wr: begin
+					buffer = {buffer, io3, io2, io1, io0};
+					bitcount = bitcount + 4;
+					if (bitcount == 8) begin
+						bitcount = 0;
+						bytecount = bytecount + 1;
+						spi_action;
+					end
+				end
+				mode_qspi_ddr_rd: begin
+					ddr_rd_edge;
+				end
+				mode_qspi_ddr_wr: begin
+					ddr_wr_edge;
+				end
+			endcase
+		end
+	end
+endmodule
diff --git a/verilog/dv/harness/mgmt_soc/start.s b/verilog/dv/harness/mgmt_soc/start.s
new file mode 100644
index 0000000..62a6f42
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/start.s
@@ -0,0 +1,159 @@
+.section .text
+
+start:
+
+# zero-initialize register file
+addi x1, zero, 0
+# x2 (sp) is initialized by reset
+addi x3, zero, 0
+addi x4, zero, 0
+addi x5, zero, 0
+addi x6, zero, 0
+addi x7, zero, 0
+addi x8, zero, 0
+addi x9, zero, 0
+addi x10, zero, 0
+addi x11, zero, 0
+addi x12, zero, 0
+addi x13, zero, 0
+addi x14, zero, 0
+addi x15, zero, 0
+addi x16, zero, 0
+addi x17, zero, 0
+addi x18, zero, 0
+addi x19, zero, 0
+addi x20, zero, 0
+addi x21, zero, 0
+addi x22, zero, 0
+addi x23, zero, 0
+addi x24, zero, 0
+addi x25, zero, 0
+addi x26, zero, 0
+addi x27, zero, 0
+addi x28, zero, 0
+addi x29, zero, 0
+addi x30, zero, 0
+addi x31, zero, 0
+
+# zero initialize scratchpad memory
+# setmemloop:
+# sw zero, 0(x1)
+# addi x1, x1, 4
+# blt x1, sp, setmemloop
+
+# copy data section
+la a0, _sidata
+la a1, _sdata
+la a2, _edata
+bge a1, a2, end_init_data
+loop_init_data:
+lw a3, 0(a0)
+sw a3, 0(a1)
+addi a0, a0, 4
+addi a1, a1, 4
+blt a1, a2, loop_init_data
+end_init_data:
+
+# zero-init bss section
+la a0, _sbss
+la a1, _ebss
+bge a0, a1, end_init_bss
+loop_init_bss:
+sw zero, 0(a0)
+addi a0, a0, 4
+blt a0, a1, loop_init_bss
+end_init_bss:
+
+# call main
+call main
+loop:
+j loop
+
+.global flashio_worker_begin
+.global flashio_worker_end
+
+.balign 4
+
+flashio_worker_begin:
+# a0 ... data pointer
+# a1 ... data length
+# a2 ... optional WREN cmd (0 = disable)
+
+# address of SPI ctrl reg
+li   t0, 0x28000000
+
+# Set CS high, IO0 is output
+li   t1, 0x120
+sh   t1, 0(t0)
+
+# Enable Manual SPI Ctrl
+sb   zero, 3(t0)
+
+# Send optional WREN cmd
+beqz a2, flashio_worker_L1
+li   t5, 8
+andi t2, a2, 0xff
+flashio_worker_L4:
+srli t4, t2, 7
+sb   t4, 0(t0)
+ori  t4, t4, 0x10
+sb   t4, 0(t0)
+slli t2, t2, 1
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L4
+sb   t1, 0(t0)
+
+# SPI transfer
+flashio_worker_L1:
+
+# If byte count is zero, we're done
+beqz a1, flashio_worker_L3
+
+# Set t5 to count down 32 bits
+li   t5, 32
+# Load t2 from address a0 (4 bytes)
+lw   t2, 0(a0)
+
+flashio_worker_LY:
+# Set t6 to count down 8 bits
+li   t6, 8
+
+flashio_worker_L2:
+# Clock out the bit (msb first) on IO0 and read bit in from IO1
+srli t4, t2, 31
+sb   t4, 0(t0)
+ori  t4, t4, 0x10
+sb   t4, 0(t0)
+lbu  t4, 0(t0)
+andi t4, t4, 2
+srli t4, t4, 1
+slli t2, t2, 1
+or   t2, t2, t4
+
+# Decrement 32 bit count
+addi t5, t5, -1
+bnez t5, flashio_worker_LX
+
+sw   t2, 0(a0)
+addi a0, a0, 4
+lw   t2, 0(a0)
+
+flashio_worker_LX:
+addi t6, t6, -1
+bnez t6, flashio_worker_L2
+addi a1, a1, -1
+bnez a1, flashio_worker_LY
+
+beqz t5, flashio_worker_L3
+sw   t2, 0(a0)
+
+flashio_worker_L3:
+# Back to MEMIO mode
+li   t1, 0x80
+sb   t1, 3(t0)
+
+ret
+.balign 4
+flashio_worker_end:
+
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/Makefile b/verilog/dv/harness/mgmt_soc/sysctrl/Makefile
new file mode 100644
index 0000000..0b43365
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/sysctrl/Makefile
@@ -0,0 +1,33 @@
+.SUFFIXES:
+
+PATTERN = sysctrl
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c ../sections.lds ../start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+
+%.hex: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c
new file mode 100644
index 0000000..a4a6762
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c
@@ -0,0 +1,43 @@
+#include "../defs.h"
+
+// --------------------------------------------------------
+
+/*
+	System Control Test
+        - Reads default value of SPI-Controlled registers
+        - Flags failure/success using gpio
+*/
+void main()
+{
+	int i;
+
+    reg_gpio_data = 0;
+	reg_gpio_ena =  0x0000;
+
+	// start test
+	reg_gpio_data = 0xA040;
+
+    // Read Product ID value
+    if(0x05 != reg_spi_prod_id) reg_gpio_data = 0xAB40;
+	reg_gpio_data = 0xAB41;
+
+    // Read Manufacturer ID value
+    if(0x456 != reg_spi_mfgr_id) reg_gpio_data = 0xAB50;
+	reg_gpio_data = 0xAB51;
+
+    // Read Mask revision 
+    if(0x1 != reg_spi_mask_rev) reg_gpio_data = 0xAB60;
+	reg_gpio_data = 0xAB61;
+
+    // Read PLL-Bypass
+    if(0x1 != reg_spi_pll_bypass) reg_gpio_data = 0xAB70;
+	reg_gpio_data = 0xAB71;
+
+    if(0x7FFDFFF != reg_spi_pll_config) reg_gpio_data = 0xAB80;
+	reg_gpio_data = 0xAB81;
+
+    // Read spi enables
+    if(0x83 != reg_spi_enables) reg_gpio_data = 0xAB90;
+	reg_gpio_data = 0xAB91;
+}
+
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v
new file mode 100644
index 0000000..d1e4439
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -0,0 +1,170 @@
+
+`timescale 1 ns / 1 ps
+
+`include "harness.v"
+`include "spiflash.v"
+
+module sysctrl_tb;
+	reg XCLK;
+	reg XI;
+
+	reg real adc_h, adc_l;
+	reg real adc_0, adc_1;
+	reg real comp_n, comp_p;
+	reg SDI, CSB, SCK, RSTB;
+
+	wire [15:0] gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+	wire SDO;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #10 XCLK <= (XCLK === 1'b0);
+	always #220 XI <= (XI === 1'b0);
+
+	initial begin
+		XI = 0;
+		XCLK = 0;
+	end
+
+	initial begin
+		$dumpfile("sysctrl_tb.vcd");
+		$dumpvars(0, sysctrl_tb);
+		repeat (25) begin
+			repeat (1000) @(posedge XCLK);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+		 $display("%c[0m",27);
+		$finish;
+	end
+
+	always @(gpio) begin
+		if(gpio == 16'hA040) begin
+			$display("System control Test started");
+		end
+		else if(gpio == 16'hAB40) begin
+			$display("%c[1;31m",27);
+			$display("Monitor: System control (RTL) Test failed");
+			$display("%c[0m",27);
+			$finish;
+		end
+		else if(gpio == 16'hAB41) begin
+			$display("Monitor: System control product ID read passed");
+		end
+        else if(gpio == 16'hAB50) begin
+            $display("%c[1;31m",27);
+			$display("Monitor: System control manufacture ID read failed");
+			$display("%c[0m",27);
+			$finish;
+        end else if(gpio == 16'hAB51) begin
+			$display("Monitor: System control manufacture ID read passed");
+        end
+        else if(gpio == 16'hAB60) begin
+            $display("%c[1;31m",27);
+			$display("Monitor: System control mask rev read failed");
+			$display("%c[0m",27);
+			$finish;
+        end else if(gpio == 16'hAB61) begin
+			$display("Monitor: System control mask rev read passed");
+        end
+        else if(gpio == 16'hAB70) begin
+            $display("%c[1;31m",27);
+			$display("Monitor: System control pll-bypass read failed");
+			$display("%c[0m",27);
+			$finish;
+        end else if(gpio == 16'hAB71) begin
+			$display("Monitor: System control pll-bypass read passed");
+        end
+        else if(gpio == 16'hAB80) begin
+            $display("%c[1;31m",27);
+			$display("Monitor: System control pll-config read failed");
+			$display("%c[0m",27);
+			$finish;
+        end else if(gpio == 16'hAB81) begin
+			$display("Monitor: System control pll-config read passed");
+        end
+        else if(gpio == 16'hAB90) begin
+            $display("%c[1;31m",27);
+			$display("Monitor: System control spi-enables read failed");
+			$display("%c[0m",27);
+			$finish;
+        end else if(gpio == 16'hAB91) begin
+			$display("Monitor: System control spi-enables read passed");
+			$display("Monitor: Sysctrl (RTL) test passed.");
+            $finish;
+        end
+	end
+
+	initial begin
+		CSB <= 1'b1;
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+		CSB <= 1'b0;	    // Apply CSB to start transmission
+	end
+
+	always @(gpio) begin
+		#1 $display("GPIO state = %b ", gpio);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+	
+	assign VSS = 1'b0;
+	assign VDD1V8 = 1'b1;
+	assign VDD3V3 = 1'b1;
+
+	harness uut (
+		.vdd	  (VDD3V3),
+		.vdd1v8	  (VDD1V8),
+		.vss	  (VSS),
+		.xi	      (XI),
+		.xclk	  (XCLK),
+		.SDI	  (SDI),
+		.SDO	  (SDO),
+		.CSB	  (CSB),
+		.SCK	  (SCK),
+		.ser_rx	  (1'b0),
+		.ser_tx	  (),
+		.irq	  (1'b0),
+		.gpio     (gpio),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.flash_io2(flash_io2),
+		.flash_io3(flash_io3),
+		.adc_high (adc_h),
+		.adc_low  (adc_l),
+		.adc0_in  (adc_0),
+		.adc1_in  (adc_1),
+		.RSTB	  (RSTB),
+		.comp_inp (comp_p),
+		.comp_inn (comp_n)
+	);
+
+	spiflash #(
+		.FILENAME("sysctrl.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(flash_io2),
+		.io3(flash_io3)
+	);
+
+endmodule
diff --git a/verilog/dv/harness/mgmt_soc/tbuart.v b/verilog/dv/harness/mgmt_soc/tbuart.v
new file mode 100644
index 0000000..97c4283
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/tbuart.v
@@ -0,0 +1,89 @@
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+/* tbuart --- mimic an external UART display, operating at 9600 baud	*/
+/* and accepting ASCII characters for display.				*/
+
+/* To do:  Match a known UART 3.3V 16x2 LCD display.  However, it	*/
+/* should be possible on a testing system to interface to the UART	*/
+/* pins on a Raspberry Pi, also running at 3.3V.			*/
+
+module tbuart (
+	input  ser_rx
+);
+	reg [3:0] recv_state;
+	reg [2:0] recv_divcnt;
+	reg [7:0] recv_pattern;
+	reg [8*50-1:0] recv_buf_data;	// 50 characters.  Increase as needed for tests.
+
+	reg clk;
+
+	initial begin
+		clk <= 1'b0;
+		recv_state <= 0;
+		recv_divcnt <= 0;
+		recv_pattern <= 0;
+		recv_buf_data <= 0;
+	end
+
+	// NOTE:  Running at 3.0us clock period @ 5 clocks per bit = 15.0us per
+	// bit ~= 64 kbaud. Not tuned to any particular UART.  Most run at
+	// 9600 baud default and will bounce up to higher baud rates when
+	// passed specific command words.
+
+	always #1500 clk <= (clk === 1'b0);
+
+	always @(posedge clk) begin
+		recv_divcnt <= recv_divcnt + 1;
+		case (recv_state)
+			0: begin
+				if (!ser_rx)
+					recv_state <= 1;
+				recv_divcnt <= 0;
+			end
+			1: begin
+				if (2*recv_divcnt > 3'd3) begin
+					recv_state <= 2;
+					recv_divcnt <= 0;
+				end
+			end
+			10: begin
+				if (recv_divcnt > 3'd3) begin
+					// 0x0a = '\n'
+					if (recv_pattern == 8'h0a) begin
+						$display("output: %s", recv_buf_data);
+					end else begin
+						recv_buf_data <= {recv_buf_data, recv_pattern};
+					end
+					recv_state <= 0;
+				end
+			end
+			default: begin
+				if (recv_divcnt > 3'd3) begin
+					recv_pattern <= {ser_rx, recv_pattern[7:1]};
+					recv_state <= recv_state + 1;
+					recv_divcnt <= 0;
+				end
+			end
+		endcase
+	end
+
+endmodule
diff --git a/verilog/dv/harness/mgmt_soc/uart/Makefile b/verilog/dv/harness/mgmt_soc/uart/Makefile
new file mode 100644
index 0000000..057be64
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/uart/Makefile
@@ -0,0 +1,35 @@
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+
+PATTERN = uart
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c ../sections.lds ../start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+
+%.hex: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/verilog/dv/harness/mgmt_soc/uart/uart.c b/verilog/dv/harness/mgmt_soc/uart/uart.c
new file mode 100644
index 0000000..fe362f8
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/uart/uart.c
@@ -0,0 +1,41 @@
+#include "../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+	if (c == '\n')
+		putchar('\r');
+	reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+	while (*p)
+		putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+	// Set clock to 64 kbaud
+	reg_uart_clkdiv = 625;
+
+	// NOTE: XCLK is running in simulation at 40MHz
+	// Divided by clkdiv is 64 kHz
+	// So at this crystal rate, use clkdiv = 4167 for 9600 baud.
+
+	/* All GPIO pins are configured to be output */
+	reg_gpio_data = 0;
+	reg_gpio_ena =  0x0000;
+
+	// start test
+	reg_gpio_data = 0xA000;
+
+	// This should appear at the output, received by the testbench UART.
+    print("\n");
+	print("Monitor: Test UART (RTL) passed\n\n");
+	reg_gpio_data = 0xAB00;
+}
+
diff --git a/verilog/dv/harness/mgmt_soc/uart/uart_tb.v b/verilog/dv/harness/mgmt_soc/uart/uart_tb.v
new file mode 100644
index 0000000..56c76f2
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/uart/uart_tb.v
@@ -0,0 +1,154 @@
+/*
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "harness.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module uart_tb;
+	reg XCLK;
+	reg XI;
+
+	reg real adc_h, adc_l;
+	reg real adc_0, adc_1;
+	reg real comp_n, comp_p;
+	reg SDI, CSB, SCK, RSTB;
+
+	wire [15:0] gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+	wire SDO;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 XCLK <= (XCLK === 1'b0);
+	always #220 XI <= (XI === 1'b0);
+
+	initial begin
+		XI = 0;
+		XCLK = 0;
+	end
+
+	initial begin
+		// Analog input pin values (static)
+		adc_h = 0.0;
+		adc_l = 0.0;
+		adc_0 = 0.0;
+		adc_1 = 0.0;
+		comp_n = 0.0;
+		comp_p = 0.0;
+	end
+
+	initial begin
+		$dumpfile("uart.vcd");
+		$dumpvars(0, uart_tb);
+
+		$display("Wait for UART o/p");
+		repeat (150) begin
+			repeat (10000) @(posedge XCLK);
+			// Diagnostic. . . interrupts output pattern.
+		end
+		$finish;
+	end
+
+	initial begin
+		CSB <= 1'b1;
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+		CSB <= 1'b0;
+	end
+
+	always @(gpio) begin
+		if(gpio == 16'hA000) begin
+			$display("UART Test started");
+		end
+		else if(gpio == 16'hAB00) begin
+			#1000;
+			$finish;
+		end
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VSS = 1'b0;
+	assign VDD1V8 = 1'b1;
+	assign VDD3V3 = 1'b1;
+
+	harness uut (
+		.vdd	  (VDD3V3),
+		.vdd1v8	  (VDD1V8),
+		.vss	  (VSS),
+		.xi	  	  (XI),
+		.xo	      (),
+		.xclk	  (XCLK),
+		.SDI	  (SDI),
+		.SDO	  (SDO),
+		.CSB	  (CSB),
+		.SCK	  (SCK),
+		.ser_rx	  (1'b0),
+		.ser_tx	  (tbuart_rx),
+		.irq	  (1'b0),
+		.gpio     (gpio),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.flash_io2(flash_io2),
+		.flash_io3(flash_io3),
+		.adc_high (adc_h),
+		.adc_low  (adc_l),
+		.adc0_in  (adc_0),
+		.adc1_in  (adc_1),
+		.RSTB	  (RSTB),
+		.comp_inp (comp_p),
+		.comp_inn (comp_n)
+	);
+
+	spiflash #(
+		.FILENAME("uart.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(flash_io2),
+		.io3(flash_io3)
+	);
+
+	// Testbench UART
+	tbuart tbuart (
+		.ser_rx(tbuart_rx)
+	);
+		
+endmodule
diff --git a/verilog/dv/harness/mgmt_soc/verify.log b/verilog/dv/harness/mgmt_soc/verify.log
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/verify.log
diff --git a/verilog/dv/harness/mgmt_soc/xbar/Makefile b/verilog/dv/harness/mgmt_soc/xbar/Makefile
new file mode 100644
index 0000000..5302d06
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/xbar/Makefile
@@ -0,0 +1,32 @@
+.SUFFIXES:
+
+PATTERN = xbar
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c ../sections.lds ../start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+
+%.hex: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/harness/mgmt_soc/xbar/xbar.c b/verilog/dv/harness/mgmt_soc/xbar/xbar.c
new file mode 100644
index 0000000..5565f1f
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/xbar/xbar.c
@@ -0,0 +1,41 @@
+#include "../defs.h"
+
+// --------------------------------------------------------
+
+/*
+	Crosbbar Switch Test
+        - Reads default value of SPI-Controlled registers
+        - Flags failure/success using gpio
+*/
+void main()
+{
+	int i;
+
+    reg_gpio_data = 0;
+	reg_gpio_ena =  0x0000;
+
+	// start test
+	reg_gpio_data = 0xA040;
+
+    // Write & Read from QSPI CTRL Slave
+    qspi_ctrl_slave = 0xA0A1; 
+    if(0xA0A1 != qspi_ctrl_slave) reg_gpio_data = 0xAB40;
+	reg_gpio_data = 0xAB41;
+
+    // Write & Read from storage area Slave
+    storage_area_slave = 0xB0B1; 
+    if(0xB0B1 != storage_area_slave) reg_gpio_data = 0xAB50;
+	reg_gpio_data = 0xAB51;
+
+    // Write & Read from Mega Project 1st slave
+    mega_any_slave1 = 0xC0C1; 
+    if(0xC0C1 != mega_any_slave1) reg_gpio_data = 0xAB60;
+	reg_gpio_data = 0xAB61;
+
+    // Write & Read from Mega Project 1st slave
+    mega_any_slave2 = 0xD0D1; 
+    if(0xD0D1 != mega_any_slave2) reg_gpio_data = 0xAB70;
+	reg_gpio_data = 0xAB71;
+
+}
+
diff --git a/verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v b/verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v
new file mode 100644
index 0000000..b9357f0
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v
@@ -0,0 +1,150 @@
+
+`timescale 1 ns / 1 ps
+
+`include "harness.v"
+`include "spiflash.v"
+
+module xbar_tb;
+	reg XCLK;
+	reg XI;
+
+	reg real adc_h, adc_l;
+	reg real adc_0, adc_1;
+	reg real comp_n, comp_p;
+	reg SDI, CSB, SCK, RSTB;
+
+	wire [15:0] gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+	wire SDO;
+
+	always #10 XCLK <= (XCLK === 1'b0);
+	always #220 XI <= (XI === 1'b0);
+
+	initial begin
+		XI = 0;
+		XCLK = 0;
+	end
+
+	initial begin
+		$dumpfile("xbar_tb.vcd");
+		$dumpvars(0, xbar_tb);
+		repeat (25) begin
+			repeat (1000) @(posedge XCLK);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Timeout, Test Crossbar Switch (RTL) Failed");
+		 $display("%c[0m", 27);
+		$finish;
+	end
+
+	always @(gpio) begin
+		if(gpio == 16'hA040) begin
+			$display("Crossbar Switch Test started");
+		end
+		else if(gpio == 16'hAB40) begin
+			$display("%c[1;31m",27);
+			$display("Monitor: Crossbar test R/W from QSPI CTRL slave failed.");
+			$display("%c[0m",27);
+			$finish;
+		end
+		else if(gpio == 16'hAB41) begin
+			$display("Monitor: Crossbar test R/W from QSPI CTRL slave passed");
+		end
+        else if(gpio == 16'hAB50) begin
+            $display("%c[1;31m",27);
+			$display("Monitor: Crossbar test R/W from storage area failed.");
+			$display("%c[0m",27);
+			$finish;
+        end else if(gpio == 16'hAB51) begin
+			$display("Monitor: Crossbar test R/W from storage area passed.");
+        end
+        else if(gpio == 16'hAB60) begin
+            $display("%c[1;31m",27);
+			$display("Monitor: Crossbar test R/W from mega project 1st slave failed.");
+			$display("%c[0m",27);
+			$finish;
+        end else if(gpio == 16'hAB61) begin
+			$display("Monitor: Crossbar test R/W from mega project 1st slave passed.");
+        end
+        else if(gpio == 16'hAB70) begin
+            $display("%c[1;31m",27);
+			$display("Monitor: Crossbar test R/W from mega project 2nd slave passed.");
+			$display("%c[0m",27);
+			$finish;
+        end else if(gpio == 16'hAB71) begin
+			$display("Monitor: Crossbar test R/W from mega project 2nd slave passed.");
+		    $display("Monitor: Timeout, Test Crossbar Switch (RTL) Passed.");
+            $finish;
+        end
+	end
+
+	initial begin
+		CSB <= 1'b1;
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+		CSB <= 1'b0;	    // Apply CSB to start transmission
+	end
+
+	always @(gpio) begin
+		#1 $display("GPIO state = %b ", gpio);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+	
+	assign VSS = 1'b0;
+	assign VDD1V8 = 1'b1;
+	assign VDD3V3 = 1'b1;
+
+	harness uut (
+		.vdd	  (VDD3V3),
+		.vdd1v8	  (VDD1V8),
+		.vss	  (VSS),
+		.xi	  (XI),
+		.xclk	  (XCLK),
+		.SDI	  (SDI),
+		.SDO	  (SDO),
+		.CSB	  (CSB),
+		.SCK	  (SCK),
+		.ser_rx	  (1'b0),
+		.ser_tx	  (),
+		.irq	  (1'b0),
+		.gpio     (gpio),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.flash_io2(flash_io2),
+		.flash_io3(flash_io3),
+		.adc_high (adc_h),
+		.adc_low  (adc_l),
+		.adc0_in  (adc_0),
+		.adc1_in  (adc_1),
+		.RSTB	  (RSTB),
+		.comp_inp (comp_p),
+		.comp_inn (comp_n)
+	);
+
+	spiflash #(
+		.FILENAME("xbar.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(flash_io2),
+		.io3(flash_io3)
+	);
+
+endmodule
diff --git a/verilog/dv/wb/Makefile b/verilog/dv/wb/Makefile
new file mode 100644
index 0000000..7b0e09b
--- /dev/null
+++ b/verilog/dv/wb/Makefile
@@ -0,0 +1,18 @@
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = gpio_wb intercon_wb  spimemio_wb uart_wb  crossbar_wb arbiter_wb
+
+all:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+	done
+
+clean:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make clean ) ; \
+	done
+
+.PHONY: clean all
diff --git a/verilog/dv/wb/arbiter_wb/Makefile b/verilog/dv/wb/arbiter_wb/Makefile
new file mode 100644
index 0000000..e792a4d
--- /dev/null
+++ b/verilog/dv/wb/arbiter_wb/Makefile
@@ -0,0 +1,17 @@
+.SUFFIXES:
+
+PATTERN = arbiter_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog -I ../../../ip -I .. -I ../../ -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/wb/arbiter_wb/arbiter_wb_tb.v b/verilog/dv/wb/arbiter_wb/arbiter_wb_tb.v
new file mode 100644
index 0000000..164d526
--- /dev/null
+++ b/verilog/dv/wb/arbiter_wb/arbiter_wb_tb.v
@@ -0,0 +1,232 @@
+
+`timescale 1 ns / 1 ps
+
+`include "arbiter.v"
+`include "dummy_slave.v"
+
+`ifndef AW
+`define AW 32
+`endif
+`ifndef DW
+`define DW 32
+`endif
+`ifndef NM
+`define NM 2
+`endif
+
+module arbiter_wb_tb;
+    
+    localparam SEL = `DW / 8;
+
+    reg wb_clk_i;
+    reg wb_rst_i;
+
+    // Masters Interface
+    reg [`NM-1:0] wbm_stb_i;
+    reg [`NM-1:0] wbm_cyc_i;
+    reg [`NM-1:0] wbm_we_i;
+    reg [`NM*SEL-1:0] wbm_sel_i;
+    reg [`NM*`DW-1:0] wbm_dat_i;
+    reg [`NM*`AW-1:0] wbm_adr_i;
+
+    wire [`NM-1:0] wbm_ack_o;
+    wire [`NM-1:0] wbm_err_o;
+    wire [`NM*`DW-1:0] wbm_dat_o;
+
+    // Slave Interface
+    reg  wbs_ack_i;
+    reg  wbs_err_i;               
+    wire [`DW-1:0] wbs_dat_i;      
+    wire wbs_stb_i;
+    wire wbs_cyc_i;           
+    wire wbs_we_i;    
+    wire [SEL-1:0] wbs_sel_i;      
+    wire [`AW-1:0] wbs_adr_i;   
+    wire [`DW-1:0] wbs_dat_o; 
+
+    wb_arbiter  #(
+        .AW(`AW),
+        .DW(`DW),
+        .NM(`NM)
+    ) uut (
+        .wb_clk_i(wb_clk_i),
+        .wb_rst_i(wb_rst_i),
+
+        // Masters Interface
+        .wbm_stb_i(wbm_stb_i),
+        .wbm_cyc_i(wbm_cyc_i),
+        .wbm_we_i(wbm_we_i),
+        .wbm_sel_i(wbm_sel_i),
+        .wbm_dat_i(wbm_dat_i),
+        .wbm_adr_i(wbm_adr_i),
+
+        .wbm_ack_o(wbm_ack_o),
+        .wbm_err_o(wbm_err_o),
+        .wbm_dat_o(wbm_dat_o),
+
+        // Slave Interface
+        .wbs_ack_i(wbs_ack_o), 
+        .wbs_err_i(wbs_err_o),               
+        .wbs_dat_i(wbs_dat_o),      
+        .wbs_stb_o(wbs_stb_i),   
+        .wbs_cyc_o(wbs_cyc_i),           
+        .wbs_we_o(wbs_we_i),     
+        .wbs_sel_o(wbs_sel_i),       
+        .wbs_adr_o(wbs_adr_i),   
+        .wbs_dat_o(wbs_dat_i)  
+    );
+    
+    // Instantiate one dummy slave for testing
+    dummy_slave dummy_slave (
+        .wb_clk_i(wb_clk_i),
+        .wb_rst_i(wb_rst_i),
+        .wb_stb_i(wbs_stb_i),
+        .wb_cyc_i(wbs_cyc_i),
+        .wb_we_i(wbs_we_i),
+        .wb_sel_i(wbs_sel_i),
+        .wb_adr_i(wbs_adr_i),
+        .wb_dat_i(wbs_dat_i),
+        .wb_dat_o(wbs_dat_o),
+        .wb_ack_o(wbs_ack_o)
+    );
+    
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    initial begin
+        wb_clk_i  = 0;
+        wb_rst_i  = 0;
+        wbm_stb_i = 0;
+        wbm_cyc_i = 0;
+        wbm_we_i  = 0;
+        wbm_sel_i = 0;
+        wbm_dat_i = 0;
+        wbm_adr_i = 0;
+        wbs_ack_i = 0; 
+        wbs_err_i = 0;               
+    end
+
+    initial begin
+        $dumpfile("arbiter_wb_tb.vcd");
+        $dumpvars(0, arbiter_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Arbiter Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+
+    reg [`DW-1:0] data;
+    reg [`AW-1:0] address;
+
+    integer i;
+
+    initial begin
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0;
+        #2;
+
+        // Case 1: Initiate W/R requests from M0 -- MN
+        for (i=0; i<`NM; i=i+1) begin
+            data = $urandom_range(0, 255);
+            address = $urandom_range(0, 255);
+            write(address,data,i);
+            #2;
+            read(i);
+            if (wbm_dat_i[i*`DW +: `DW] !== data) begin
+                $display("Request Error from master %0b", i);
+                $finish;
+            end
+        end 
+
+        #10;
+
+        // Case 2: Initiate W/R requests from MN -- M0
+        for (i=`NM-1; i>=0; i=i-1) begin
+            data = $urandom_range(0, 255);
+            address = $urandom_range(0, 255);
+            write(address,data,i);
+            #2;
+            read(i);
+            if (wbm_dat_i[i*`DW +: `DW] !== data) begin
+                $display("Request Error from master %0b", i);
+                $finish;
+            end
+        end 
+
+        // Case 3: Initiate concurrent W/R requests from all masters
+        address = $urandom_range(0, 255);
+        wbm_stb_i = {`NM{1'b1}};
+        wbm_cyc_i = {`NM{1'b1}};
+        wbm_we_i  = {`NM{1'b1}};
+        wbm_sel_i = {`NM{4'hF}};
+        wbm_adr_i = {`NM{address}};
+        for (i=`NM-1; i>=0; i=i-1) begin
+            wbm_dat_i[i*`DW+: `DW] = $urandom_range(0, 2**32);
+        end
+
+        // Make sure that served request is master 0 (highest priority)      
+        wait(wbm_ack_o[0]);
+        if (wbm_ack_o[`NM-1:1] !== 0) begin
+          $display("Arbitration failed");
+          $finish;
+        end
+
+        // Read
+        wbm_we_i  = {`NM{1'b0}};
+        wait(wbm_ack_o[0]);
+       
+        // Make sure that the second master doesn't receive an ack
+        if (wbm_ack_o[`NM-1:1] !== 0) begin
+          $display("Arbitration failed");
+          $finish;
+        end        
+        #10;
+        $finish;
+    end
+
+    task read;
+        input mindex;
+        begin 
+            @(posedge wb_clk_i) begin
+                wbm_stb_i[mindex] = 1;
+                wbm_cyc_i[mindex] = 1;
+                wbm_we_i[mindex]  = 0;
+                $display("Read Cycle from master %0b started", mindex);
+            end
+            wait(wbm_ack_o[mindex]);
+            wait(!wbm_ack_o[mindex]);
+            wbm_stb_i[mindex] = 0;
+            wbm_cyc_i[mindex] = 0;
+            $display("Read Cycle from master %0b ended.", mindex);
+        end
+    endtask
+
+    task write;
+        input [`AW-1:0] adr;
+        input [`DW-1:0] data;
+        input integer mindex;
+
+        begin 
+            @(posedge wb_clk_i) begin
+                wbm_stb_i[mindex] = 1;
+                wbm_cyc_i[mindex] = 1;
+                wbm_we_i[mindex]  = 1;
+                wbm_sel_i[mindex*SEL+: SEL] = {SEL{1'b1}};
+                wbm_adr_i[mindex*`AW+: `AW] = adr;
+                wbm_dat_i[mindex*`DW+: `DW] = data;
+                $display("Write Cycle from master %0b started", mindex);
+            end
+           
+            wait(wbm_ack_o[mindex]);
+            wait(!wbm_ack_o[mindex]);
+            wbm_stb_i[mindex] = 0;
+            wbm_cyc_i[mindex] = 0;
+            $display("Write Cycle from master %0b ended.", mindex);
+        end
+    endtask
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/crossbar_wb/Makefile b/verilog/dv/wb/crossbar_wb/Makefile
new file mode 100644
index 0000000..fcd10cc
--- /dev/null
+++ b/verilog/dv/wb/crossbar_wb/Makefile
@@ -0,0 +1,17 @@
+.SUFFIXES:
+
+PATTERN = crossbar_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog  -I .. -I ../../ -I ../../../ip -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/wb/crossbar_wb/crossbar_wb_tb.v b/verilog/dv/wb/crossbar_wb/crossbar_wb_tb.v
new file mode 100644
index 0000000..a9a35b4
--- /dev/null
+++ b/verilog/dv/wb/crossbar_wb/crossbar_wb_tb.v
@@ -0,0 +1,292 @@
+
+`timescale 1 ns / 1 ps
+
+`include "crossbar.v"
+`include "dummy_slave.v"
+
+`ifndef AW
+    `define AW 32
+`endif
+`ifndef DW
+    `define DW 32
+`endif
+`ifndef NM
+    `define NM 2
+`endif
+
+`ifndef NS
+    `define NS 4
+`endif
+
+`ifndef SLAVE_ADR
+    `define SLAVE_ADR { \
+        {8'hB0, {24{1'b0}}},\
+        {8'hA0, {24{1'b0}}},\
+        {8'h90, {24{1'b0}}},\
+        {8'h80, {24{1'b0}}}\
+    }\
+`endif
+
+`ifndef ADR_MASK
+    `define ADR_MASK { \
+        {8'hFF, {24{1'b0}}}, \
+        {8'hFF, {24{1'b0}}}, \
+        {8'hFF, {24{1'b0}}}, \
+        {8'hFF, {24{1'b0}}}  \
+    }\
+`endif
+
+module crossbar_wb_tb;
+
+    localparam SEL = `DW / 8;
+
+    reg wb_clk_i;           
+    reg wb_rst_i;     
+
+    // Masters interface
+    reg [`NM-1:0] wbm_cyc_i;       
+    reg [`NM-1:0] wbm_stb_i;       
+    reg [`NM-1:0] wbm_we_i;     
+    reg [(`NM*(`DW/8))-1:0] wbm_sel_i;     
+    reg [(`NM*`AW)-1:0] wbm_adr_i;        
+    reg [(`NM*`DW)-1:0] wbm_dat_i;       
+    wire [`NM-1:0] wbm_ack_o; 
+    wire [`NM-1:0] wbm_err_o;       
+    wire [(`NM*`DW)-1:0] wbm_dat_o;       
+
+    // Slaves interfaces
+    wire [`NS-1:0] wbs_ack_o;       
+    wire [(`NS*`DW)-1:0] wbs_dat_i;
+    wire [`NS-1:0] wbs_cyc_o;        
+    wire [`NS-1:0] wbs_stb_o;       
+    wire [`NS-1:0] wbs_we_o;        
+    wire [(`NS*(`DW/8))-1:0] wbs_sel_o;       
+    wire [(`NS*`AW)-1:0] wbs_adr_o;       
+    wire [(`NS*`DW)-1:0] wbs_dat_o;  
+    
+    wb_xbar #(
+        .NM(`NM),
+        .NS(`NS),
+        .AW(`AW),
+        .DW(`DW),
+        .SLAVE_ADR(`SLAVE_ADR),
+        .ADR_MASK(`ADR_MASK) 
+    )
+    wb_xbar(
+        .wb_clk_i(wb_clk_i),           
+        .wb_rst_i(wb_rst_i),     
+        // Masters interface
+        .wbm_cyc_i(wbm_cyc_i),       
+        .wbm_stb_i(wbm_stb_i),       
+        .wbm_we_i (wbm_we_i),     
+        .wbm_sel_i(wbm_sel_i),     
+        .wbm_adr_i(wbm_adr_i),        
+        .wbm_dat_i(wbm_dat_i),       
+        .wbm_ack_o(wbm_ack_o), 
+        .wbm_dat_o(wbm_dat_o),       
+        // Slaves interfaces
+        .wbs_ack_i(wbs_ack_o),       
+        .wbs_dat_i(wbs_dat_o),
+        .wbs_cyc_o(wbs_cyc_o),        
+        .wbs_stb_o(wbs_stb_o),       
+        .wbs_we_o(wbs_we_o),        
+        .wbs_sel_o(wbs_sel_o),       
+        .wbs_adr_o(wbs_adr_o),       
+        .wbs_dat_o(wbs_dat_i)     
+    );
+
+    // Instantiate four dummy slaves for testing
+    dummy_slave dummy_slaves [`NS-1:0](
+        .wb_clk_i({`NS{wb_clk_i}}),
+        .wb_rst_i({`NS{wb_rst_i}}),
+        .wb_stb_i(wbs_stb_o),
+        .wb_cyc_i(wbs_cyc_o),
+        .wb_we_i(wbs_we_o),
+        .wb_sel_i(wbs_sel_o),
+        .wb_adr_i(wbs_adr_o),
+        .wb_dat_i(wbs_dat_i),
+        .wb_dat_o(wbs_dat_o),
+        .wb_ack_o(wbs_ack_o)
+    );
+
+    initial begin
+        wb_clk_i  = 0;           
+        wb_rst_i  = 0;     
+        wbm_cyc_i = 0;       
+        wbm_stb_i = 0;       
+        wbm_we_i  = 0;     
+        wbm_sel_i = 0;     
+        wbm_adr_i = 0;        
+        wbm_dat_i = 0;  
+    end
+   
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    initial begin
+        $dumpfile("crossbar_wb_tb.vcd");
+        $dumpvars(0, crossbar_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Crossbar Switch Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    reg [`AW*`NS-1:0] addresses = {
+        {8'hB0, {24{1'b0}}},
+        {8'hA0, {24{1'b0}}},
+        {8'h90, {24{1'b0}}},
+        {8'h80, {24{1'b0}}}
+    };
+
+    reg [`DW-1:0] m0_slave_data;
+    reg [`DW-1:0] m1_slave_data;
+    reg [`AW-1:0] slave_adr;
+
+    initial begin
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0;
+        #2;
+
+        // Case 1: Master0 addresses slave 0 and Master 2 Addresses slave 1
+        slave_adr = addresses[`AW-1:0];
+        m0_slave_data = $urandom_range(0, 2**(`DW-2));
+        write(slave_adr, m0_slave_data, 0);
+
+        #2;
+        read(slave_adr, 0);
+        if (wbm_dat_o[0*`DW+: `DW] !== m0_slave_data) begin
+            $display("Error reading from slave");
+            $finish;
+        end
+        
+        #10;
+        slave_adr = addresses[`AW*2-1:`AW*1];
+        m1_slave_data = $urandom_range(0, 2**(`DW-2));
+        write(slave_adr, m1_slave_data, 1);
+        #2;
+        read(slave_adr, 1);
+        #10;
+        if (wbm_dat_o[1*`DW+: `DW] !== m1_slave_data) begin
+            $display("Error reading from slave");
+            $finish;
+        end
+        #10;
+        // Case 2: Master0 addresses slave 0 and Master 2 Addresses slave 1 simultaenously
+        slave_adr = addresses[`AW-1:0];
+        m0_slave_data = $urandom_range(0, 2**(`DW-2));
+
+        wbm_stb_i[0] = 1;
+        wbm_cyc_i[0] = 1;
+        wbm_we_i [0]  = 1;
+        wbm_sel_i[0*SEL+: SEL] = {SEL{1'b1}};
+        wbm_adr_i[0*`AW+: `AW] = slave_adr;
+        wbm_dat_i[0*`DW+: `DW] = m0_slave_data;
+
+        slave_adr = addresses[`AW*2-1:`AW*1];
+        m1_slave_data = $urandom_range(0, 2**(`DW-2));
+
+        wbm_stb_i[1] = 1;
+        wbm_cyc_i[1] = 1;
+        wbm_we_i[1]  = 1;
+        wbm_sel_i[1*SEL+: SEL] = {SEL{1'b1}};
+        wbm_adr_i[1*`AW+: `AW] = slave_adr;
+        wbm_dat_i[1*`DW+: `DW] = m1_slave_data;
+
+        wait(wbm_ack_o[0] && wbm_ack_o[1]);
+        wait(!wbm_ack_o[0] && !wbm_ack_o[1]);
+        
+        // Read
+        wbm_we_i  = 2'b00;
+        wait(wbm_ack_o[0] && wbm_ack_o[1]);
+        wait(!wbm_ack_o[0] && !wbm_ack_o[1]);
+
+        if (wbm_dat_o[0*`DW+: `DW] !== m0_slave_data) begin
+            $display("Error reading from slave");
+            $finish;
+        end
+       
+        // Case 3: Master0 addresses slave 0 and Master 2 Addresses slave 1 simultaenously
+        slave_adr = addresses[`AW-1:0];
+        m0_slave_data = $urandom_range(0, 2**(`DW-2));
+
+        wbm_stb_i[0] = 1;
+        wbm_cyc_i[0] = 1;
+        wbm_we_i [0]  = 1;
+        wbm_sel_i[0*SEL+: SEL] = {SEL{1'b1}};
+        wbm_adr_i[0*`AW+: `AW] = slave_adr;
+        wbm_dat_i[0*`DW+: `DW] = m0_slave_data;
+
+        slave_adr = addresses[`AW-1:0];
+        m1_slave_data = $urandom_range(0, 2**(`DW-2));
+
+        wbm_stb_i[1] = 1;
+        wbm_cyc_i[1] = 1;
+        wbm_we_i [1]  = 1;
+        wbm_sel_i[1*SEL+: SEL] = {SEL{1'b1}};
+        wbm_adr_i[1*`AW+: `AW] = slave_adr;
+        wbm_dat_i[1*`DW+: `DW] = m1_slave_data;
+
+        wait(wbm_ack_o[0] && !wbm_ack_o[1]);
+        wait(!wbm_ack_o[0] && !wbm_ack_o[1]);
+        
+        // Read
+        wbm_we_i  = 2'b00;
+        wait(wbm_ack_o[0]);
+        wait(!wbm_ack_o[0]);
+        if (wbm_dat_o[0*`DW+: `DW] !== m0_slave_data) begin
+            $display("Error reading from slave");
+            $finish;
+        end
+
+        $finish;
+    end
+
+    task read;
+        input addr;
+        input mindex;
+        begin 
+            @(posedge wb_clk_i) begin
+                wbm_stb_i[mindex] = 1;
+                wbm_cyc_i[mindex] = 1;
+                wbm_we_i[mindex]  = 0;
+                $display("Read cycle from master %0b started", mindex);
+            end
+            wait(wbm_ack_o[mindex]);
+            wait(!wbm_ack_o[mindex]);
+            wbm_stb_i[mindex] = 0;
+            wbm_cyc_i[mindex] = 0;
+            $display("Read cycle from master %0b ended.", mindex);
+        end
+    endtask
+
+    task write;
+        input [`AW-1:0] adr;
+        input [`DW-1:0] data;
+        input integer mindex;
+
+        begin 
+            @(posedge wb_clk_i) begin
+                wbm_stb_i[mindex] = 1;
+                wbm_cyc_i[mindex] = 1;
+                wbm_we_i[mindex]  = 1;
+                wbm_sel_i[mindex*SEL+: SEL] = {SEL{1'b1}};
+                wbm_adr_i[mindex*`AW+: `AW] = adr;
+                wbm_dat_i[mindex*`DW+: `DW] = data;
+                $display("Write cycle from master %0b started", mindex);
+            end
+           
+            wait(wbm_ack_o[mindex]);
+            wait(!wbm_ack_o[mindex]);
+            wbm_stb_i[mindex] = 0;
+            wbm_cyc_i[mindex] = 0;
+            $display("Write cycle from master %0b ended.", mindex);
+        end
+    endtask
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/distributor/Makefile b/verilog/dv/wb/distributor/Makefile
new file mode 100644
index 0000000..f3a1273
--- /dev/null
+++ b/verilog/dv/wb/distributor/Makefile
@@ -0,0 +1,17 @@
+.SUFFIXES:
+
+PATTERN = distributor
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog  -I .. -I ../../ -I ../../../ip -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/wb/distributor/distributor_tb.v b/verilog/dv/wb/distributor/distributor_tb.v
new file mode 100644
index 0000000..ab8f929
--- /dev/null
+++ b/verilog/dv/wb/distributor/distributor_tb.v
@@ -0,0 +1,226 @@
+
+`timescale 1 ns / 1 ps
+
+`include "distributor.v"
+`include "dummy_slave.v"
+
+`ifndef AW
+    `define AW 32
+`endif
+`ifndef DW
+    `define DW 32
+`endif
+
+`ifndef NS
+    `define NS 4
+`endif
+
+`ifndef SLAVE_ADR
+    `define SLAVE_ADR { \
+        {8'hB0, {24{1'b0}}},\
+        {8'hA0, {24{1'b0}}},\
+        {8'h90, {24{1'b0}}},\
+        {8'h80, {24{1'b0}}}\
+    }\
+`endif
+
+`ifndef ADR_MASK
+    `define ADR_MASK { \
+        {8'hFF, {24{1'b0}}}, \
+        {8'hFF, {24{1'b0}}}, \
+        {8'hFF, {24{1'b0}}}, \
+        {8'hFF, {24{1'b0}}}  \
+    }\
+`endif
+
+module distributor_tb;
+
+    localparam SEL = `DW / 8;
+
+    reg wb_clk_i;           
+    reg wb_rst_i;     
+
+    // Masters interface
+    reg wbm_cyc_i;       
+    reg wbm_stb_i;       
+    reg wbm_we_i;     
+    reg [(`DW/8)-1:0] wbm_sel_i;     
+    reg [`AW-1:0] wbm_adr_i;        
+    reg [`DW-1:0] wbm_dat_i;       
+    wire wbm_ack_o; 
+    wire [`DW-1:0] wbm_dat_o;       
+
+    // Slaves interfaces
+    wire [`NS-1:0] wbs_ack_o;       
+    wire [(`NS*`DW)-1:0] wbs_dat_i;
+    wire [`NS-1:0] wbs_cyc_o;        
+    wire [`NS-1:0] wbs_stb_o;       
+    wire [`NS-1:0] wbs_we_o;        
+    wire [(`NS*(`DW/8))-1:0] wbs_sel_o;       
+    wire [(`NS*`AW)-1:0] wbs_adr_o;       
+    wire [(`NS*`DW)-1:0] wbs_dat_o;  
+    
+    distributor #(
+        .NS(`NS),
+        .AW(`AW),
+        .DW(`DW),
+        .ADR_MASK(`ADR_MASK),
+        .SLAVE_ADR(`SLAVE_ADR)
+    )
+    uut (
+        .wb_clk_i(wb_clk_i),           
+        .wb_rst_i(wb_rst_i),     
+        // Masters interface
+        .wbm_cyc_i(wbm_cyc_i),       
+        .wbm_stb_i(wbm_stb_i),       
+        .wbm_we_i (wbm_we_i),     
+        .wbm_sel_i(wbm_sel_i),     
+        .wbm_adr_i(wbm_adr_i),        
+        .wbm_dat_i(wbm_dat_i),       
+        .wbm_ack_o(wbm_ack_o), 
+        .wbm_dat_o(wbm_dat_o),
+
+        // Slaves interfaces
+        .wbs_ack_i(wbs_ack_o),       
+        .wbs_dat_i(wbs_dat_o),
+        .wbs_cyc_o(wbs_cyc_o),        
+        .wbs_stb_o(wbs_stb_o),       
+        .wbs_we_o(wbs_we_o),        
+        .wbs_sel_o(wbs_sel_o),       
+        .wbs_adr_o(wbs_adr_o),       
+        .wbs_dat_o(wbs_dat_i)     
+    );
+
+    // Instantiate four dummy slaves for testing
+    dummy_slave dummy_slaves [`NS-1:0](
+        .wb_clk_i({`NS{wb_clk_i}}),
+        .wb_rst_i({`NS{wb_rst_i}}),
+        .wb_stb_i(wbs_stb_o),
+        .wb_cyc_i(wbs_cyc_o),
+        .wb_we_i(wbs_we_o),
+        .wb_sel_i(wbs_sel_o),
+        .wb_adr_i(wbs_adr_o),
+        .wb_dat_i(wbs_dat_i),
+        .wb_dat_o(wbs_dat_o),
+        .wb_ack_o(wbs_ack_o)
+    );
+
+    initial begin
+        wb_clk_i  = 0;           
+        wb_rst_i  = 0;     
+        wbm_cyc_i = 0;       
+        wbm_stb_i = 0;       
+        wbm_we_i  = 0;     
+        wbm_sel_i = 0;     
+        wbm_adr_i = 0;        
+        wbm_dat_i = 0;  
+    end
+   
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    initial begin
+        $dumpfile("distributor_tb.vcd");
+        $dumpvars(0, distributor_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Distributor Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    reg [`DW-1:0] slave_data;
+    reg [`AW-1:0] slave_adr;
+
+    initial begin
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0;
+        #2;
+        
+        slave_adr = 32'h 8000_0000;
+        slave_data = $urandom_range(0, 2**(`DW-2));
+        write(slave_adr, slave_data);
+        #2;
+        read(slave_adr);
+        if (wbm_dat_i !== slave_data) begin
+          $display("Failed R/W from slave");
+        end
+        
+        #2;
+        slave_adr = 32'h 9000_0000;
+        slave_data = $urandom_range(0, 2**(`DW-2));
+        write(slave_adr, slave_data);
+        #2;
+        read(slave_adr);
+        if (wbm_dat_i !== slave_data) begin
+          $display("Failed R/W from slave");
+        end
+        #2;
+
+        slave_adr = 32'h A000_0000;
+        slave_data = $urandom_range(0, 2**(`DW-2));
+        write(slave_adr, slave_data);
+        #2;
+        read(slave_adr);
+        if (wbm_dat_i !== slave_data) begin
+          $display("Failed R/W from slave");
+        end
+        
+        #2;
+        slave_adr = 32'h B000_0000;
+        slave_data = $urandom_range(0, 2**(`DW-2));
+        write(slave_adr, slave_data);
+        #2;
+        read(slave_adr);
+        if (wbm_dat_i !== slave_data) begin
+          $display("Failed R/W from slave");
+        end
+
+
+        $finish;
+    end
+
+    task read;
+        input [`AW-1:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wbm_stb_i = 1;
+                wbm_cyc_i = 1;
+                wbm_we_i  = 0;
+                wbm_adr_i = addr;
+                $display("Read Cycle Started");
+            end
+            wait(wbm_ack_o);
+            wait(!wbm_ack_o);
+            wbm_stb_i = 0;
+            wbm_cyc_i = 0;
+            $display("Read cycle Ended");
+        end
+    endtask
+
+    task write;
+        input [`AW-1:0] adr;
+        input [`DW-1:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wbm_stb_i = 1;
+                wbm_cyc_i = 1;
+                wbm_we_i  = 1;
+                wbm_sel_i = {SEL{1'b1}};
+                wbm_adr_i = adr;
+                wbm_dat_i = data;
+                $display("Write cycle started");
+            end
+            wait(wbm_ack_o);
+            wait(!wbm_ack_o);
+            wbm_stb_i = 0;
+            wbm_cyc_i = 0;
+            $display("Write cycle ended.");
+        end
+    endtask
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/distributor/distributor_tb.vcd b/verilog/dv/wb/distributor/distributor_tb.vcd
new file mode 100644
index 0000000..12f7ae8
--- /dev/null
+++ b/verilog/dv/wb/distributor/distributor_tb.vcd
@@ -0,0 +1,963 @@
+$date
+	Fri Aug 21 14:18:15 2020
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module distributor_tb $end
+$var wire 4 ! wbs_we_o [3:0] $end
+$var wire 4 " wbs_stb_o [3:0] $end
+$var wire 16 # wbs_sel_o [15:0] $end
+$var wire 128 $ wbs_dat_o [127:0] $end
+$var wire 128 % wbs_dat_i [127:0] $end
+$var wire 4 & wbs_cyc_o [3:0] $end
+$var wire 128 ' wbs_adr_o [127:0] $end
+$var wire 4 ( wbs_ack_o [3:0] $end
+$var wire 32 ) wbm_dat_o [31:0] $end
+$var wire 1 * wbm_ack_o $end
+$var reg 32 + slave_adr [31:0] $end
+$var reg 32 , slave_data [31:0] $end
+$var reg 1 - wb_clk_i $end
+$var reg 1 . wb_rst_i $end
+$var reg 32 / wbm_adr_i [31:0] $end
+$var reg 1 0 wbm_cyc_i $end
+$var reg 32 1 wbm_dat_i [31:0] $end
+$var reg 4 2 wbm_sel_i [3:0] $end
+$var reg 1 3 wbm_stb_i $end
+$var reg 1 4 wbm_we_i $end
+$scope module dummy_slaves[0] $end
+$var wire 1 5 valid $end
+$var wire 32 6 wb_adr_i [31:0] $end
+$var wire 1 7 wb_clk_i $end
+$var wire 1 8 wb_cyc_i $end
+$var wire 32 9 wb_dat_i [31:0] $end
+$var wire 1 : wb_rst_i $end
+$var wire 4 ; wb_sel_i [3:0] $end
+$var wire 1 < wb_stb_i $end
+$var wire 1 = wb_we_i $end
+$var reg 32 > store [31:0] $end
+$var reg 1 ? wb_ack_o $end
+$var reg 32 @ wb_dat_o [31:0] $end
+$upscope $end
+$scope module dummy_slaves[1] $end
+$var wire 1 A valid $end
+$var wire 32 B wb_adr_i [31:0] $end
+$var wire 1 C wb_clk_i $end
+$var wire 1 D wb_cyc_i $end
+$var wire 32 E wb_dat_i [31:0] $end
+$var wire 1 F wb_rst_i $end
+$var wire 4 G wb_sel_i [3:0] $end
+$var wire 1 H wb_stb_i $end
+$var wire 1 I wb_we_i $end
+$var reg 32 J store [31:0] $end
+$var reg 1 K wb_ack_o $end
+$var reg 32 L wb_dat_o [31:0] $end
+$upscope $end
+$scope module dummy_slaves[2] $end
+$var wire 1 M valid $end
+$var wire 32 N wb_adr_i [31:0] $end
+$var wire 1 O wb_clk_i $end
+$var wire 1 P wb_cyc_i $end
+$var wire 32 Q wb_dat_i [31:0] $end
+$var wire 1 R wb_rst_i $end
+$var wire 4 S wb_sel_i [3:0] $end
+$var wire 1 T wb_stb_i $end
+$var wire 1 U wb_we_i $end
+$var reg 32 V store [31:0] $end
+$var reg 1 W wb_ack_o $end
+$var reg 32 X wb_dat_o [31:0] $end
+$upscope $end
+$scope module dummy_slaves[3] $end
+$var wire 1 Y valid $end
+$var wire 32 Z wb_adr_i [31:0] $end
+$var wire 1 [ wb_clk_i $end
+$var wire 1 \ wb_cyc_i $end
+$var wire 32 ] wb_dat_i [31:0] $end
+$var wire 1 ^ wb_rst_i $end
+$var wire 4 _ wb_sel_i [3:0] $end
+$var wire 1 ` wb_stb_i $end
+$var wire 1 a wb_we_i $end
+$var reg 32 b store [31:0] $end
+$var reg 1 c wb_ack_o $end
+$var reg 32 d wb_dat_o [31:0] $end
+$upscope $end
+$scope module uut $end
+$var wire 1 - wb_clk_i $end
+$var wire 1 . wb_rst_i $end
+$var wire 32 e wbm_adr_i [31:0] $end
+$var wire 1 0 wbm_cyc_i $end
+$var wire 32 f wbm_dat_i [31:0] $end
+$var wire 4 g wbm_sel_i [3:0] $end
+$var wire 1 3 wbm_stb_i $end
+$var wire 1 4 wbm_we_i $end
+$var wire 4 h wbs_ack_i [3:0] $end
+$var wire 4 i wbs_cyc_o [3:0] $end
+$var wire 128 j wbs_dat_i [127:0] $end
+$var wire 4 k wbs_stb_o [3:0] $end
+$var wire 4 l wbs_we_o [3:0] $end
+$var wire 16 m wbs_sel_o [15:0] $end
+$var wire 128 n wbs_dat_o [127:0] $end
+$var wire 128 o wbs_adr_o [127:0] $end
+$var wire 1 * wbm_ack_o $end
+$var wire 4 p slave_sel [3:0] $end
+$var reg 32 q wbm_dat_o [31:0] $end
+$var integer 32 r i [31:0] $end
+$scope begin genblk1[0] $end
+$upscope $end
+$scope begin genblk1[1] $end
+$upscope $end
+$scope begin genblk1[2] $end
+$upscope $end
+$scope begin genblk1[3] $end
+$upscope $end
+$upscope $end
+$scope task read $end
+$var reg 32 s addr [31:0] $end
+$upscope $end
+$scope task write $end
+$var reg 32 t adr [31:0] $end
+$var reg 32 u data [31:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+bx u
+bx t
+bx s
+b10000000 r
+b0 q
+b0 p
+b0 o
+b0 n
+b0 m
+b0 l
+b0 k
+bx j
+b0 i
+bx h
+b0 g
+b0 f
+b0 e
+bx d
+xc
+bx b
+0a
+0`
+b0 _
+1^
+b0 ]
+0\
+0[
+b0 Z
+0Y
+bx X
+xW
+bx V
+0U
+0T
+b0 S
+1R
+b0 Q
+0P
+0O
+b0 N
+0M
+bx L
+xK
+bx J
+0I
+0H
+b0 G
+1F
+b0 E
+0D
+0C
+b0 B
+0A
+bx @
+x?
+bx >
+0=
+0<
+b0 ;
+1:
+b0 9
+08
+07
+b0 6
+05
+04
+03
+b0 2
+b0 1
+00
+b0 /
+1.
+0-
+bx ,
+bx +
+0*
+b0 )
+bx (
+b0 '
+b0 &
+b0 %
+bx $
+b0 #
+b0 "
+b0 !
+$end
+#1000
+0?
+0K
+0W
+b0 (
+b0 h
+0c
+17
+1C
+1O
+1[
+1-
+#2000
+07
+0C
+0O
+0[
+0:
+0F
+0R
+0^
+0-
+0.
+#3000
+17
+1C
+1O
+1[
+1-
+#4000
+07
+0C
+0O
+0[
+0-
+b100100100001010100110101001001 u
+b10000000000000000000000000000000 t
+b100100100001010100110101001001 ,
+b10000000000000000000000000000000 +
+#5000
+b100100100001010100110101001001 >
+b100100100001010100110101001001 J
+b100100100001010100110101001001 V
+b100100100001010100110101001001 b
+15
+1<
+18
+b1 "
+b1 k
+b1 &
+b1 i
+bx )
+bx q
+b10000000 r
+b100100100001010100110101001001 9
+b100100100001010100110101001001 E
+b100100100001010100110101001001 Q
+b100100100001010100110101001001 ]
+b10000000000000000000000000000000 6
+b10000000000000000000000000000000 B
+b10000000000000000000000000000000 N
+b10000000000000000000000000000000 Z
+b1 p
+b1111 ;
+b1111 G
+b1111 S
+b1111 _
+1=
+1I
+1U
+1a
+17
+1C
+1O
+1[
+b100100100001010100110101001001001001001000010101001101010010010010010010000101010011010100100100100100100001010100110101001001 %
+b100100100001010100110101001001001001001000010101001101010010010010010010000101010011010100100100100100100001010100110101001001 n
+b100100100001010100110101001001 1
+b100100100001010100110101001001 f
+b10000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000 '
+b10000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000 o
+b10000000000000000000000000000000 /
+b10000000000000000000000000000000 e
+b1111111111111111 #
+b1111111111111111 m
+b1111 2
+b1111 g
+b1111 !
+b1111 l
+14
+10
+13
+1-
+#6000
+07
+0C
+0O
+0[
+0-
+#7000
+1*
+b10000000 r
+b100100100001010100110101001001 )
+b100100100001010100110101001001 q
+b1 (
+b1 h
+1?
+b100100100001010100110101001001 @
+b100100100001010100110101001001 L
+b100100100001010100110101001001 X
+b100100100001010100110101001001001001001000010101001101010010010010010010000101010011010100100100100100100001010100110101001001 $
+b100100100001010100110101001001001001001000010101001101010010010010010010000101010011010100100100100100100001010100110101001001 j
+b100100100001010100110101001001 d
+17
+1C
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diff --git a/verilog/dv/wb/gpio_wb/Makefile b/verilog/dv/wb/gpio_wb/Makefile
new file mode 100644
index 0000000..d8d54e4
--- /dev/null
+++ b/verilog/dv/wb/gpio_wb/Makefile
@@ -0,0 +1,17 @@
+.SUFFIXES:
+
+PATTERN = gpio_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog -I .. -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/verilog/dv/wb/gpio_wb/gpio_wb_tb.v b/verilog/dv/wb/gpio_wb/gpio_wb_tb.v
new file mode 100644
index 0000000..8db196c
--- /dev/null
+++ b/verilog/dv/wb/gpio_wb/gpio_wb_tb.v
@@ -0,0 +1,182 @@
+
+
+`timescale 1 ns / 1 ps
+
+`include "gpio_wb.v"
+
+module gpio_wb_tb;
+
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    reg wb_stb_i;
+    reg wb_cyc_i;
+	reg wb_we_i;
+	reg [3:0] wb_sel_i;
+
+	reg [31:0] wb_dat_i;
+	reg [31:0] wb_adr_i;
+    reg [15:0] gpio_in_pad;
+
+	wire wb_ack_o;
+	wire [31:0] wb_dat_o;
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_stb_i = 0; 
+        wb_cyc_i = 0;  
+        wb_sel_i = 0;  
+        wb_we_i  = 0;  
+        wb_dat_i = 0; 
+        wb_adr_i = 0;  
+        gpio_in_pad = 0;
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    initial begin
+        $dumpfile("gpio_wb_tb.vcd");
+        $dumpvars(0, gpio_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test GPIO Wishbone Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+    
+    // GPIO Internal Register Addresses
+    wire [31:0] gpio_adr     = uut.BASE_ADR | uut.GPIO_DATA;
+    wire [31:0] gpio_oeb_adr = uut.BASE_ADR | uut.GPIO_ENA;
+    wire [31:0] gpio_pu_adr  = uut.BASE_ADR | uut.GPIO_PU;
+    wire [31:0] gpio_pd_adr  = uut.BASE_ADR | uut.GPIO_PD;
+
+    reg [15:0] gpio_data;
+    reg [15:0] gpio_pu; 
+    reg [15:0] gpio_pd; 
+    reg [15:0] gpio_oeb;  
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0; 
+        #2;
+
+        // Write to gpio_data reg
+        gpio_in_pad = 16'h FFFF;
+        gpio_data = 16'h A000;
+        write(gpio_adr, gpio_data);
+       
+        #2;
+        // Read from gpio_data reg
+        read(gpio_adr);
+        if (wb_dat_o !== {gpio_data, gpio_in_pad}) begin
+            $display("Monitor: Error reading from gpio reg");
+            $finish;
+        end
+        
+        #2;
+        // Write to pull-up reg
+        gpio_pu = 16'h 000f;
+        write(gpio_pu_adr, gpio_pu);
+        
+        #2;
+        // Read from pull-up reg
+        read(gpio_pu_adr);
+        if (wb_dat_o !== {16'd0, gpio_pu}) begin
+            $display("Monitor: Error reading from gpio pull-up reg");
+            $finish;
+        end
+
+        #2;
+        // Write to pull-down reg
+        gpio_pd = 16'h 00f0;
+        write(gpio_pd_adr, gpio_pd);
+        
+        #2;
+        // Read from pull-down reg
+        read(gpio_pd_adr);
+        if (wb_dat_o !== {16'd0, gpio_pd}) begin
+            $display("Monitor: Error reading from gpio pull-down reg");
+            $finish;
+        end
+
+        #2;
+        // Write to gpio enable reg
+        gpio_oeb = 16'h 00ff;
+        write(gpio_oeb_adr, gpio_oeb);
+        
+        #2;
+        // Read from gpio enable reg
+        read(gpio_oeb_adr);
+        if (wb_dat_o !== {16'd0, gpio_oeb}) begin
+            $display("Monitor: Error reading from gpio output enable reg");
+            $finish;
+        end
+        
+        #6;
+        $display("Monitor: GPIO WB Success!");
+        $finish;
+    end
+    
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF; 
+                wb_we_i = 1;     
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Read Cycle Ended.");
+        end
+    endtask
+    
+    gpio_wb uut(
+        .wb_clk_i(wb_clk_i),
+	    .wb_rst_i(wb_rst_i),
+        .wb_stb_i(wb_stb_i),
+	    .wb_cyc_i(wb_cyc_i),
+	    .wb_sel_i(wb_sel_i),
+	    .wb_we_i(wb_we_i),
+	    .wb_dat_i(wb_dat_i),
+	    .wb_adr_i(wb_adr_i), 
+        .wb_ack_o(wb_ack_o),
+	    .wb_dat_o(wb_dat_o),
+        .gpio_in_pad(gpio_in_pad)
+    );
+    
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/intercon_wb/Makefile b/verilog/dv/wb/intercon_wb/Makefile
new file mode 100644
index 0000000..e061e8d
--- /dev/null
+++ b/verilog/dv/wb/intercon_wb/Makefile
@@ -0,0 +1,17 @@
+.SUFFIXES:
+
+PATTERN = intercon_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog -I .. -I ../../ -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/wb/intercon_wb/intercon_wb_tb.v b/verilog/dv/wb/intercon_wb/intercon_wb_tb.v
new file mode 100644
index 0000000..14702f9
--- /dev/null
+++ b/verilog/dv/wb/intercon_wb/intercon_wb_tb.v
@@ -0,0 +1,187 @@
+
+
+`timescale 1 ns / 1 ps
+
+`include "wb_intercon.v"
+`include "dummy_slave.v"
+
+`define AW 32
+`define DW 32
+`define NS 6
+
+`define SLAVE_ADR { \
+    {8'h28, {24{1'b0}} }, \   
+    {8'h23, {24{1'b0}} }, \     
+    {8'h21, {24{1'b0}} }, \    
+    {8'h20, {24{1'b0}} }, \    
+    {8'h10, {24{1'b0}} }, \    
+    {8'h00, {24{1'b0}} }  \
+}\
+
+`define ADR_MASK { \
+    {8'hFF, {24{1'b0}} }, \
+    {8'hFF, {24{1'b0}} }, \
+    {8'hFF, {24{1'b0}} }, \
+    {8'hFF, {24{1'b0}} }, \
+    {8'hFF, {24{1'b0}} }, \
+    {8'hFF, {24{1'b0}} }  \
+}\
+
+module intercon_wb_tb;
+
+    localparam SEL = `DW / 8;
+
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    // Master Interface
+    reg wbm_stb_i;
+    reg wbm_cyc_i;
+    reg wbm_we_i;
+    reg [SEL-1:0] wbm_sel_i;
+    reg [`AW-1:0] wbm_adr_i;
+    reg [`DW-1:0] wbm_dat_i;
+
+    wire [`DW-1:0] wbm_dat_o;
+    wire wbm_ack_o;
+
+    // Wishbone Slave Interface
+    wire [`NS-1:0] wbs_stb_i;
+    wire [`NS-1:0] wbs_ack_o;
+    wire [(`NS*`DW)-1:0] wbs_adr_i;
+    wire [(`NS*`AW)-1:0] wbs_dat_i;
+    wire [(`NS*`DW)-1:0] wbs_dat_o;
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wbm_adr_i = 0;  
+        wbm_dat_i = 0;  
+        wbm_sel_i = 0;   
+        wbm_we_i  = 0;    
+        wbm_cyc_i = 0;   
+        wbm_stb_i = 0;  
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    initial begin
+        $dumpfile("intercon_wb_tb.vcd");
+        $dumpvars(0, intercon_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Wishbone Interconnect Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    reg [`AW*`NS-1: 0] addr = `SLAVE_ADR;
+    reg [`DW:0] slave_data;
+    reg [`AW:0] slave_addr;
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0; 
+        #2;
+
+        // W/R from all slaves
+        for (i=0; i<`NS; i=i+1) begin
+            slave_addr = addr[i*`AW +: `AW];
+            slave_data = $urandom_range(0, 2**32);
+            write(slave_addr, slave_data);
+            #2;
+            read(slave_addr);
+            if (wbm_dat_o !== slave_data) begin
+                $display("%c[1;31m",27);
+                $display ("Monitor: Reading from slave %0d failed", i);
+                $display("Monitor: Test Wishbone Interconnect failed");
+                $display("%c[0m",27);
+                $finish;
+            end
+        end
+        $display("Monitor: Test Wishbone Interconnect Success!");
+        $finish;
+    end
+    
+    task write;
+        input [`AW-1:0] addr;
+        input [`AW-1:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wbm_stb_i = 1;
+                wbm_cyc_i = 1;
+                wbm_sel_i = {SEL{1'b1}}; 
+                wbm_we_i = 1;    
+                wbm_adr_i = addr;
+                wbm_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wbm_ack_o == 1);
+            wait(wbm_ack_o == 0);
+            wbm_cyc_i = 0;
+            wbm_stb_i = 0;
+            $display("Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [`AW-1:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wbm_stb_i = 1;
+                wbm_cyc_i = 1;
+                wbm_adr_i = addr;
+                wbm_we_i =  0;     
+                $display("Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wbm_ack_o == 1);
+            wait(wbm_ack_o == 0);
+            wbm_cyc_i = 0;
+            wbm_stb_i = 0;
+            $display("Read Cycle Ended.");
+        
+        end
+    endtask
+
+    wb_intercon #(
+        .AW(`AW),
+        .DW(`DW),
+        .NS(`NS),
+        .ADR_MASK(`ADR_MASK),
+        .SLAVE_ADR(`SLAVE_ADR)
+    ) uut(
+        // Master Interface
+        .wbm_adr_i(wbm_adr_i),
+        .wbm_stb_i(wbm_stb_i),
+        .wbm_dat_o(wbm_dat_o),
+        .wbm_ack_o(wbm_ack_o), 
+    
+        // Slave Interface
+        .wbs_stb_o(wbs_stb_i),
+        .wbs_dat_i(wbs_dat_o), 
+        .wbs_ack_i(wbs_ack_o)
+    );
+    
+    // Instantiate five dummy slaves for testing
+    dummy_slave dummy_slaves [`NS-1:0](
+        .wb_clk_i({`NS{wb_clk_i}}),
+        .wb_rst_i({`NS{wb_rst_i}}),
+        .wb_stb_i(wbs_stb_i),
+        .wb_cyc_i(wbm_cyc_i),
+        .wb_we_i(wbm_we_i),
+        .wb_sel_i(wbm_sel_i),
+        .wb_adr_i(wbm_adr_i),
+        .wb_dat_i(wbm_dat_i),
+        .wb_dat_o(wbs_dat_o),
+        .wb_ack_o(wbs_ack_o)
+    );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/la_wb/Makefile b/verilog/dv/wb/la_wb/Makefile
new file mode 100644
index 0000000..216614f
--- /dev/null
+++ b/verilog/dv/wb/la_wb/Makefile
@@ -0,0 +1,17 @@
+.SUFFIXES:
+
+PATTERN = la_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog -I .. -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/verilog/dv/wb/la_wb/la_wb_tb.v b/verilog/dv/wb/la_wb/la_wb_tb.v
new file mode 100644
index 0000000..2c50186
--- /dev/null
+++ b/verilog/dv/wb/la_wb/la_wb_tb.v
@@ -0,0 +1,208 @@
+`timescale 1 ns / 1 ps
+
+`include "la_wb.v"
+
+module la_wb_tb;
+
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    reg wb_stb_i;
+    reg wb_cyc_i;
+	reg wb_we_i;
+	reg [3:0] wb_sel_i;
+
+	reg [31:0] wb_dat_i;
+	reg [31:0] wb_adr_i;
+
+	wire wb_ack_o;
+	wire [31:0] wb_dat_o;
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_stb_i = 0; 
+        wb_cyc_i = 0;  
+        wb_sel_i = 0;  
+        wb_we_i  = 0;  
+        wb_dat_i = 0; 
+        wb_adr_i = 0;  
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+    
+    initial begin
+        $dumpfile("la_wb_tb.vcd");
+        $dumpvars(0, la_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Wishbone LA Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+    
+    // LA Wishbone Internal Register Addresses
+    wire [31:0] la_data_adr_0   = uut.BASE_ADR | uut.LA_DATA_0;
+    wire [31:0] la_data_adr_1   = uut.BASE_ADR | uut.LA_DATA_1;
+    wire [31:0] la_data_adr_2   = uut.BASE_ADR | uut.LA_DATA_2;
+    wire [31:0] la_data_adr_3   = uut.BASE_ADR | uut.LA_DATA_3;
+    
+    wire [31:0] la_ena_adr_0 = uut.BASE_ADR | uut.LA_ENA_0;
+    wire [31:0] la_ena_adr_1 = uut.BASE_ADR | uut.LA_ENA_1;
+    wire [31:0] la_ena_adr_2 = uut.BASE_ADR | uut.LA_ENA_2;
+    wire [31:0] la_ena_adr_3 = uut.BASE_ADR | uut.LA_ENA_3;
+
+    reg [31:0] la_data_0;
+    reg [31:0] la_data_1; 
+    reg [31:0] la_data_2;
+    reg [31:0] la_data_3; 
+
+    reg [31:0] la_ena_0;
+    reg [31:0] la_ena_1; 
+    reg [31:0] la_ena_2;
+    reg [31:0] la_ena_3; 
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0; 
+        #2;
+
+        // Write to la data registers
+        la_data_0 = $urandom_range(0, 2**32);
+        la_data_1 = $urandom_range(0, 2**32);
+        la_data_2 = $urandom_range(0, 2**32);
+        la_data_3 = $urandom_range(0, 2**32);
+
+        write(la_data_adr_0, la_data_0);
+        write(la_data_adr_1, la_data_1);
+        write(la_data_adr_2, la_data_2);
+        write(la_data_adr_3, la_data_3);
+
+        #2;
+        // Read from la data registers
+        read(la_data_adr_0);
+        if (wb_dat_o !== la_data_0) begin
+            $display("Monitor: Error reading from la data_0 reg");
+            $finish;
+        end
+        
+        read(la_data_adr_1);
+        if (wb_dat_o !== la_data_1) begin
+            $display("Monitor: Error reading from la data_0 reg");
+            $finish;
+        end
+        
+        read(la_data_adr_2);
+        if (wb_dat_o !== la_data_1) begin
+            $display("Monitor: Error reading from la data_0 reg");
+            $finish;
+        end
+
+        read(la_data_adr_3);
+        if (wb_dat_o !== la_data_3) begin
+            $display("Monitor: Error reading from la data_0 reg");
+            $finish;
+        end
+
+        // Write to la emable registers
+        la_ena_0 = $urandom_range(0, 2**32);
+        la_ena_1 = $urandom_range(0, 2**32);
+        la_ena_2 = $urandom_range(0, 2**32);
+        la_ena_3 = $urandom_range(0, 2**32);
+
+        write(la_ena_adr_0, la_ena_0);
+        write(la_ena_adr_1, la_ena_1);
+        write(la_ena_adr_2, la_ena_2);
+        write(la_ena_adr_3, la_ena_3);
+
+        #2;
+        // Read from la data registers
+        read(la_ena_adr_0);
+        if (wb_dat_o !== la_ena_0) begin
+            $display("Monitor: Error reading from la data_0 reg");
+            $finish;
+        end
+        
+        read(la_ena_adr_1);
+        if (wb_dat_o !== la_ena_1) begin
+            $display("Monitor: Error reading from la data_0 reg");
+            $finish;
+        end
+        
+        read(la_ena_adr_2);
+        if (wb_dat_o !== la_ena_1) begin
+            $display("Monitor: Error reading from la data_0 reg");
+            $finish;
+        end
+
+        read(la_ena_adr_3);
+        if (wb_dat_o !== la_ena_3) begin
+            $display("Monitor: Error reading from la data_0 reg");
+            $finish;
+        end
+        #6;
+        $display("Monitor: Test LA Wishbone Success!");
+        $finish;
+    end
+    
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF; 
+                wb_we_i = 1;     
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Read Cycle Ended.");
+        end
+    endtask
+
+    la_wb uut(
+        .wb_clk_i(wb_clk_i),
+	    .wb_rst_i(wb_rst_i),
+        .wb_stb_i(wb_stb_i),
+	    .wb_cyc_i(wb_cyc_i),
+	    .wb_sel_i(wb_sel_i),
+	    .wb_we_i(wb_we_i),
+	    .wb_dat_i(wb_dat_i),
+	    .wb_adr_i(wb_adr_i), 
+        .wb_ack_o(wb_ack_o),
+	    .wb_dat_o(wb_dat_o)
+    );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/la_wb/la_wb_tb.vcd b/verilog/dv/wb/la_wb/la_wb_tb.vcd
new file mode 100644
index 0000000..9a9969d
--- /dev/null
+++ b/verilog/dv/wb/la_wb/la_wb_tb.vcd
@@ -0,0 +1,635 @@
+$date
+	Fri Aug 21 14:19:50 2020
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module la_wb_tb $end
+$var wire 32 ! la_data_adr_0 [31:0] $end
+$var wire 32 " la_data_adr_1 [31:0] $end
+$var wire 32 # la_data_adr_2 [31:0] $end
+$var wire 32 $ la_data_adr_3 [31:0] $end
+$var wire 32 % la_ena_adr_0 [31:0] $end
+$var wire 32 & la_ena_adr_1 [31:0] $end
+$var wire 32 ' la_ena_adr_2 [31:0] $end
+$var wire 32 ( la_ena_adr_3 [31:0] $end
+$var wire 32 ) wb_dat_o [31:0] $end
+$var wire 1 * wb_ack_o $end
+$var reg 32 + la_data_0 [31:0] $end
+$var reg 32 , la_data_1 [31:0] $end
+$var reg 32 - la_data_2 [31:0] $end
+$var reg 32 . la_data_3 [31:0] $end
+$var reg 32 / la_ena_0 [31:0] $end
+$var reg 32 0 la_ena_1 [31:0] $end
+$var reg 32 1 la_ena_2 [31:0] $end
+$var reg 32 2 la_ena_3 [31:0] $end
+$var reg 32 3 wb_adr_i [31:0] $end
+$var reg 1 4 wb_clk_i $end
+$var reg 1 5 wb_cyc_i $end
+$var reg 32 6 wb_dat_i [31:0] $end
+$var reg 1 7 wb_rst_i $end
+$var reg 4 8 wb_sel_i [3:0] $end
+$var reg 1 9 wb_stb_i $end
+$var reg 1 : wb_we_i $end
+$scope module uut $end
+$var wire 4 ; iomem_we [3:0] $end
+$var wire 1 < resetn $end
+$var wire 1 = valid $end
+$var wire 1 * wb_ack_o $end
+$var wire 32 > wb_adr_i [31:0] $end
+$var wire 1 4 wb_clk_i $end
+$var wire 1 5 wb_cyc_i $end
+$var wire 32 ? wb_dat_i [31:0] $end
+$var wire 1 7 wb_rst_i $end
+$var wire 4 @ wb_sel_i [3:0] $end
+$var wire 1 9 wb_stb_i $end
+$var wire 1 : wb_we_i $end
+$var wire 32 A wb_dat_o [31:0] $end
+$var wire 1 B ready $end
+$var wire 128 C la_ena [127:0] $end
+$var wire 128 D la_data [127:0] $end
+$scope module la_ctrl $end
+$var wire 1 4 clk $end
+$var wire 32 E iomem_addr [31:0] $end
+$var wire 1 = iomem_valid $end
+$var wire 32 F iomem_wdata [31:0] $end
+$var wire 4 G iomem_wstrb [3:0] $end
+$var wire 1 < resetn $end
+$var wire 4 H la_ena_sel [3:0] $end
+$var wire 128 I la_ena [127:0] $end
+$var wire 4 J la_data_sel [3:0] $end
+$var wire 128 K la_data [127:0] $end
+$var reg 32 L iomem_rdata [31:0] $end
+$var reg 1 B iomem_ready $end
+$var reg 32 M la_data_0 [31:0] $end
+$var reg 32 N la_data_1 [31:0] $end
+$var reg 32 O la_data_2 [31:0] $end
+$var reg 32 P la_data_3 [31:0] $end
+$var reg 32 Q la_ena_0 [31:0] $end
+$var reg 32 R la_ena_1 [31:0] $end
+$var reg 32 S la_ena_2 [31:0] $end
+$var reg 32 T la_ena_3 [31:0] $end
+$upscope $end
+$upscope $end
+$scope task read $end
+$var reg 33 U addr [32:0] $end
+$upscope $end
+$scope task write $end
+$var reg 33 V addr [32:0] $end
+$var reg 33 W data [32:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+bx W
+bx V
+bx U
+bx T
+bx S
+bx R
+bx Q
+bx P
+bx O
+bx N
+bx M
+bx L
+bx K
+b1 J
+bx I
+b0 H
+b0 G
+b0 F
+b0 E
+bx D
+bx C
+xB
+bx A
+b0 @
+b0 ?
+b0 >
+0=
+0<
+b0 ;
+0:
+09
+b0 8
+17
+b0 6
+05
+04
+b0 3
+bx 2
+bx 1
+bx 0
+bx /
+bx .
+bx -
+bx ,
+bx +
+x*
+bx )
+b100010000000000000000000011100 (
+b100010000000000000000000011000 '
+b100010000000000000000000010100 &
+b100010000000000000000000010000 %
+b100010000000000000000000001100 $
+b100010000000000000000000001000 #
+b100010000000000000000000000100 "
+b100010000000000000000000000000 !
+$end
+#1000
+b0 T
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diff --git a/verilog/dv/wb/la_wb/ldo_wb_tb.vcd b/verilog/dv/wb/la_wb/ldo_wb_tb.vcd
new file mode 100644
index 0000000..a0e252e
--- /dev/null
+++ b/verilog/dv/wb/la_wb/ldo_wb_tb.vcd
@@ -0,0 +1,635 @@
+$date
+	Thu Aug 20 00:22:06 2020
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module ldo_wb_tb $end
+$var wire 32 ! ldo_data_adr_0 [31:0] $end
+$var wire 32 " ldo_data_adr_1 [31:0] $end
+$var wire 32 # ldo_data_adr_2 [31:0] $end
+$var wire 32 $ ldo_data_adr_3 [31:0] $end
+$var wire 32 % ldo_ena_adr_0 [31:0] $end
+$var wire 32 & ldo_ena_adr_1 [31:0] $end
+$var wire 32 ' ldo_ena_adr_2 [31:0] $end
+$var wire 32 ( ldo_ena_adr_3 [31:0] $end
+$var wire 32 ) wb_dat_o [31:0] $end
+$var wire 1 * wb_ack_o $end
+$var reg 32 + ldo_data_0 [31:0] $end
+$var reg 32 , ldo_data_1 [31:0] $end
+$var reg 32 - ldo_data_2 [31:0] $end
+$var reg 32 . ldo_data_3 [31:0] $end
+$var reg 32 / ldo_ena_0 [31:0] $end
+$var reg 32 0 ldo_ena_1 [31:0] $end
+$var reg 32 1 ldo_ena_2 [31:0] $end
+$var reg 32 2 ldo_ena_3 [31:0] $end
+$var reg 32 3 wb_adr_i [31:0] $end
+$var reg 1 4 wb_clk_i $end
+$var reg 1 5 wb_cyc_i $end
+$var reg 32 6 wb_dat_i [31:0] $end
+$var reg 1 7 wb_rst_i $end
+$var reg 4 8 wb_sel_i [3:0] $end
+$var reg 1 9 wb_stb_i $end
+$var reg 1 : wb_we_i $end
+$scope module uut $end
+$var wire 4 ; iomem_we [3:0] $end
+$var wire 1 < resetn $end
+$var wire 1 = valid $end
+$var wire 1 * wb_ack_o $end
+$var wire 32 > wb_adr_i [31:0] $end
+$var wire 1 4 wb_clk_i $end
+$var wire 1 5 wb_cyc_i $end
+$var wire 32 ? wb_dat_i [31:0] $end
+$var wire 1 7 wb_rst_i $end
+$var wire 4 @ wb_sel_i [3:0] $end
+$var wire 1 9 wb_stb_i $end
+$var wire 1 : wb_we_i $end
+$var wire 32 A wb_dat_o [31:0] $end
+$var wire 1 B ready $end
+$var wire 128 C ldo_ena [127:0] $end
+$var wire 128 D ldo_data [127:0] $end
+$scope module ldo_ctrl $end
+$var wire 1 4 clk $end
+$var wire 32 E iomem_addr [31:0] $end
+$var wire 1 = iomem_valid $end
+$var wire 32 F iomem_wdata [31:0] $end
+$var wire 4 G iomem_wstrb [3:0] $end
+$var wire 1 < resetn $end
+$var wire 4 H ldo_ena_sel [3:0] $end
+$var wire 128 I ldo_ena [127:0] $end
+$var wire 4 J ldo_data_sel [3:0] $end
+$var wire 128 K ldo_data [127:0] $end
+$var reg 32 L iomem_rdata [31:0] $end
+$var reg 1 B iomem_ready $end
+$var reg 32 M ldo_data_0 [31:0] $end
+$var reg 32 N ldo_data_1 [31:0] $end
+$var reg 32 O ldo_data_2 [31:0] $end
+$var reg 32 P ldo_data_3 [31:0] $end
+$var reg 32 Q ldo_ena_0 [31:0] $end
+$var reg 32 R ldo_ena_1 [31:0] $end
+$var reg 32 S ldo_ena_2 [31:0] $end
+$var reg 32 T ldo_ena_3 [31:0] $end
+$upscope $end
+$upscope $end
+$scope task read $end
+$var reg 33 U addr [32:0] $end
+$upscope $end
+$scope task write $end
+$var reg 33 V addr [32:0] $end
+$var reg 33 W data [32:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+bx W
+bx V
+bx U
+bx T
+bx S
+bx R
+bx Q
+bx P
+bx O
+bx N
+bx M
+bx L
+bx K
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+b0 H
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+bx C
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+bx A
+b0 @
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+b0 ;
+0:
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+17
+b0 6
+05
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+b0 3
+bx 2
+bx 1
+bx 0
+bx /
+bx .
+bx -
+bx ,
+bx +
+x*
+bx )
+b100010000000000000000000011100 (
+b100010000000000000000000011000 '
+b100010000000000000000000010100 &
+b100010000000000000000000010000 %
+b100010000000000000000000001100 $
+b100010000000000000000000001000 #
+b100010000000000000000000000100 "
+b100010000000000000000000000000 !
+$end
+#1000
+b0 T
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+1:
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+0=
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+09
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+04
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+1=
+b100010000000000000000000000100 3
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+1=
+b100010000000000000000000001000 3
+b100010000000000000000000001000 >
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+b0 2
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+b1 H
+b1111 ;
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+1=
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+0=
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+09
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+1=
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diff --git a/verilog/dv/wb/mem_wb/Makefile b/verilog/dv/wb/mem_wb/Makefile
new file mode 100644
index 0000000..82b2235
--- /dev/null
+++ b/verilog/dv/wb/mem_wb/Makefile
@@ -0,0 +1,17 @@
+.SUFFIXES:
+
+PATTERN = mem_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog -I .. -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/verilog/dv/wb/mem_wb/mem_wb_tb.v b/verilog/dv/wb/mem_wb/mem_wb_tb.v
new file mode 100644
index 0000000..eb45e22
--- /dev/null
+++ b/verilog/dv/wb/mem_wb/mem_wb_tb.v
@@ -0,0 +1,143 @@
+
+
+`timescale 1 ns / 1 ps
+
+`define USE_OPENRAM
+
+`include "sram_1rw1r_32_256_8_sky130.v"
+`include "mem_wb.v"
+
+module mem_wb_tb;
+
+    reg wb_clk_i;
+    reg wb_rst_i;
+
+    reg [31:0] wb_adr_i;
+    reg [31:0] wb_dat_i;
+    reg [3:0]  wb_sel_i;
+    reg wb_we_i;
+    reg wb_cyc_i;
+    reg wb_stb_i;
+
+    wire wb_ack_o;
+    wire [31:0] wb_dat_o;
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+
+        wb_stb_i = 0;  // master select-signal for the slave
+        wb_we_i  = 0;  // R = 0 , W = 1
+        wb_cyc_i = 0;  // master is transferring
+        wb_adr_i = 0;  // input addr 32-bits
+        wb_dat_i = 0;  // input data 32-bits
+        wb_sel_i = 0;  // where data is available on data_i 4-bits
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    initial begin
+        $dumpfile("mem_wb_tb.vcd");
+        $dumpvars(0, mem_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Wishbone Memory Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    reg [31:0] ref_data [255: 0];
+    reg [31: 0] read_data;
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0; 
+        #2;
+
+        // Randomly Write to memory array
+        for ( i = 0; i < 1; i = i + 1) begin 
+            ref_data[i] = $urandom_range(0, 2**32);
+            write(i, ref_data[i]);
+            #2;
+        end
+
+        #6;
+        for ( i = 0; i < 1; i = i + 1) begin 
+            read(i);
+            if (wb_dat_o !== ref_data[i]) begin
+                $display("%c[1;31m",27);
+                $display("Expected %0b, but Got %0b ", ref_data[i], wb_dat_o);
+                $display("Monitor: Wishbone Memory Failed");
+                $display("%c[0m",27);
+                $finish;
+            end
+            #2;
+        end
+        #6;
+        $display("Success!");
+        $finish;
+    end
+     
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF; 
+                wb_we_i = 1;     
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Read Cycle Ended.");
+        end
+    endtask
+    
+    mem_wb uut(
+        .wb_clk_i(wb_clk_i),
+        .wb_rst_i(wb_rst_i),
+
+        .wb_adr_i(wb_adr_i), 
+        .wb_dat_i(wb_dat_i),
+        .wb_sel_i(wb_sel_i),
+        .wb_we_i(wb_we_i),
+        .wb_cyc_i(wb_cyc_i),
+        .wb_stb_i(wb_stb_i),
+
+        .wb_ack_o(wb_ack_o), 
+        .wb_dat_o(wb_dat_o)
+    );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/spi_sysctrl_wb/Makefile b/verilog/dv/wb/spi_sysctrl_wb/Makefile
new file mode 100644
index 0000000..55b9235
--- /dev/null
+++ b/verilog/dv/wb/spi_sysctrl_wb/Makefile
@@ -0,0 +1,18 @@
+.SUFFIXES:
+
+PATTERN = spi_sysctrl_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog  -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+
diff --git a/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.v b/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
new file mode 100644
index 0000000..0275a2c
--- /dev/null
+++ b/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
@@ -0,0 +1,226 @@
+
+
+`timescale 1 ns / 1 ps
+
+`include "spi_sysctrl.v"
+`include "striVe_spi.v"
+
+module spi_sysctrl_wb_tb;
+
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    reg wb_stb_i;
+    reg wb_cyc_i;
+	reg wb_we_i;
+	reg [3:0] wb_sel_i;
+	reg [31:0] wb_dat_i;
+	reg [31:0] wb_adr_i;
+
+	wire wb_ack_o;
+	wire [31:0] wb_dat_o;
+
+    wire [7:0] spi_ro_config; // (verify) wire input to the core not connected to HKSPI, what should it be connected to ? 
+    wire [4:0] spi_ro_pll_div; 
+    wire [2:0] spi_ro_pll_sel;
+    wire spi_ro_xtal_ena;
+    wire spi_ro_reg_ena; 
+    wire [25:0] spi_ro_pll_trim;
+    wire spi_ro_pll_dco_ena;
+    wire [11:0] spi_ro_mfgr_id;
+    wire [7:0] spi_ro_prod_id;
+    wire [3:0] spi_ro_mask_rev;
+    wire spi_ro_pll_bypass;
+   
+    // HKSPI
+    reg RSTB;	    
+    reg SCK;	   
+    reg SDI;	    
+    reg CSB;	    
+    reg trap;
+    reg [3:0] mask_rev_in;	
+
+    wire SDO;	  
+    wire sdo_enb;
+    wire xtal_ena;
+    wire reg_ena;
+    wire pll_dco_ena;
+    wire [25:0] pll_trim;
+    wire [2:0] pll_sel;
+    wire [4:0] pll_div;
+    wire pll_bypass;
+    wire irq;
+    wire reset;
+    wire RST;
+    wire [11:0] mfgr_id;
+    wire [7:0] prod_id;
+    wire [3:0] mask_rev;
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_stb_i = 0; 
+        wb_cyc_i = 0;  
+        wb_sel_i = 0;  
+        wb_we_i  = 0;  
+        wb_dat_i = 0; 
+        wb_adr_i = 0; 
+        CSB = 1;
+        SCK = 0;
+        SDI = 0;
+        RSTB = 0; 
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    // System Control Default Register Addresses (Read-only reg)
+    wire [31:0] spi_cfg         = uut.BASE_ADR | uut.SPI_CFG; // unused & reserved ? 
+    wire [31:0] spi_ena         = uut.BASE_ADR | uut.SPI_ENA;
+    wire [31:0] spi_pll_cfg     = uut.BASE_ADR | uut.SPI_PLL_CFG;
+    wire [31:0] spi_mfgr_id     = uut.BASE_ADR | uut.SPI_MFGR_ID;
+    wire [31:0] spi_prod_id     = uut.BASE_ADR | uut.SPI_PROD_ID;
+    wire [31:0] spi_mask_rev    = uut.BASE_ADR | uut.SPI_MASK_REV;
+    wire [31:0] spi_pll_bypass  = uut.BASE_ADR | uut.SPI_PLL_BYPASS;
+
+    initial begin
+        $dumpfile("spi_sysctrl_wb_tb.vcd");
+        $dumpvars(0, spi_sysctrl_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test SPI System Control Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    initial begin   
+        // Reset Operation
+        wb_rst_i = 1;
+        RSTB = 0;       // active low reset
+        #2;
+        wb_rst_i = 0;
+        RSTB = 1; 
+        #2;
+
+        // Read mask_rev register
+        mask_rev_in = 4'hF;
+        read(spi_mask_rev);
+        if (wb_dat_o !== {28'd0, mask_rev_in}) begin
+            $display("Error reading mask_rev reg");
+            $finish;
+        end
+
+        // Read manufacture id register
+        read(spi_mfgr_id);
+        if (wb_dat_o !== {20'd0, 12'h456}) begin
+            $display("Error reading manufacture id reg");
+            $finish;
+        end
+
+        // Read product id register
+        read(spi_prod_id);
+        if (wb_dat_o !== {24'd0, 8'h05}) begin
+            $display("Error reading product id reg");
+            $finish;
+        end
+
+        // Read PLL-Bypass register
+        read(spi_pll_bypass);
+        if (wb_dat_o !== {31'd0, 1'b1}) begin
+            $display("Error reading pll bypass id reg");
+            $finish;
+        end
+
+        // Read PLL-Configuration register
+        read(spi_pll_cfg);
+        if (wb_dat_o !== {5'd0, spi_ro_pll_trim, spi_ro_pll_dco_ena}) begin
+            $display("Error reading pll bypass id reg");
+            $finish;
+        end
+
+        // Read SPI Enables register
+        read(spi_ena);
+        if (wb_dat_o !== {22'd0, spi_ro_pll_div, spi_ro_pll_sel, spi_ro_xtal_ena, spi_ro_reg_ena}) begin
+            $display("Error reading pll bypass id reg");
+            $finish;
+        end                
+        $display("Success!");
+        $finish;
+    end
+
+    task read;
+        input [32:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Monitor: Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Monitor: Read Cycle Ended.");
+        end
+    endtask
+
+    spi_sysctrl_wb uut(
+        .wb_clk_i(wb_clk_i),
+	    .wb_rst_i(wb_rst_i),
+
+        .wb_stb_i(wb_stb_i),
+	    .wb_cyc_i(wb_cyc_i),
+	    .wb_sel_i(wb_sel_i),
+	    .wb_we_i(wb_we_i),
+	    .wb_dat_i(wb_dat_i),
+	    .wb_adr_i(wb_adr_i), 
+        .wb_ack_o(wb_ack_o),
+	    .wb_dat_o(wb_dat_o),
+        
+        .spi_ro_config(spi_ro_config), // (verify) wire input to the core not connected to HKSPI, what should it be connected to ? 
+        .spi_ro_pll_div(spi_ro_pll_div), 
+        .spi_ro_pll_sel(spi_ro_pll_sel),
+        .spi_ro_xtal_ena(spi_ro_xtal_ena),
+        .spi_ro_reg_ena(spi_ro_reg_ena), 
+    
+        .spi_ro_pll_trim(spi_ro_pll_trim),
+        .spi_ro_pll_dco_ena(spi_ro_pll_dco_ena),  
+
+        .spi_ro_mfgr_id(spi_ro_mfgr_id),
+        .spi_ro_prod_id(spi_ro_prod_id), 
+        .spi_ro_mask_rev(spi_ro_mask_rev), 
+        .pll_bypass(spi_ro_pll_bypass)
+    );
+
+    striVe_spi hkspi (
+		.RSTB(RSTB),
+		.SCK(SCK),
+		.SDI(SDI),
+		.CSB(CSB),
+
+		.SDO(SDO),
+		.sdo_enb(SDO_enb),
+		.xtal_ena(spi_ro_xtal_ena),
+		.reg_ena(spi_ro_reg_ena),
+		.pll_dco_ena(spi_ro_pll_dco_ena),
+		.pll_sel(spi_ro_pll_sel),
+		.pll_div(spi_ro_pll_div),
+		.pll_trim(spi_ro_pll_trim),
+		.pll_bypass(spi_ro_pll_bypass),
+		.irq(irq_spi),
+		.RST(por),
+		.reset(ext_reset),
+		.trap(trap),
+		.mfgr_id(spi_ro_mfgr_id),
+		.prod_id(spi_ro_prod_id),
+		.mask_rev_in(mask_rev_in),
+		.mask_rev(spi_ro_mask_rev)
+    );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.vcd b/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.vcd
new file mode 100644
index 0000000..3abe514
--- /dev/null
+++ b/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.vcd
@@ -0,0 +1,460 @@
+$date
+	Fri Aug 21 14:21:00 2020
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module spi_sysctrl_wb_tb $end
+$var wire 32 ! spi_cfg [31:0] $end
+$var wire 32 " spi_ena [31:0] $end
+$var wire 32 # spi_mask_rev [31:0] $end
+$var wire 32 $ spi_mfgr_id [31:0] $end
+$var wire 32 % spi_pll_bypass [31:0] $end
+$var wire 32 & spi_pll_cfg [31:0] $end
+$var wire 32 ' spi_prod_id [31:0] $end
+$var wire 8 ( spi_ro_config [7:0] $end
+$var wire 12 ) spi_ro_mfgr_id [11:0] $end
+$var wire 8 * spi_ro_prod_id [7:0] $end
+$var wire 32 + wb_dat_o [31:0] $end
+$var wire 1 , wb_ack_o $end
+$var wire 1 - spi_ro_xtal_ena $end
+$var wire 1 . spi_ro_reg_ena $end
+$var wire 26 / spi_ro_pll_trim [25:0] $end
+$var wire 3 0 spi_ro_pll_sel [2:0] $end
+$var wire 5 1 spi_ro_pll_div [4:0] $end
+$var wire 1 2 spi_ro_pll_dco_ena $end
+$var wire 1 3 spi_ro_pll_bypass $end
+$var wire 4 4 spi_ro_mask_rev [3:0] $end
+$var wire 1 5 por $end
+$var wire 1 6 irq_spi $end
+$var wire 1 7 ext_reset $end
+$var wire 1 8 SDO_enb $end
+$var wire 1 9 SDO $end
+$var reg 1 : CSB $end
+$var reg 1 ; RSTB $end
+$var reg 1 < SCK $end
+$var reg 1 = SDI $end
+$var reg 4 > mask_rev_in [3:0] $end
+$var reg 1 ? trap $end
+$var reg 32 @ wb_adr_i [31:0] $end
+$var reg 1 A wb_clk_i $end
+$var reg 1 B wb_cyc_i $end
+$var reg 32 C wb_dat_i [31:0] $end
+$var reg 1 D wb_rst_i $end
+$var reg 4 E wb_sel_i [3:0] $end
+$var reg 1 F wb_stb_i $end
+$var reg 1 G wb_we_i $end
+$scope module hkspi $end
+$var wire 1 : CSB $end
+$var wire 1 5 RST $end
+$var wire 1 ; RSTB $end
+$var wire 1 < SCK $end
+$var wire 1 = SDI $end
+$var wire 4 H mask_rev [3:0] $end
+$var wire 4 I mask_rev_in [3:0] $end
+$var wire 12 J mfgr_id [11:0] $end
+$var wire 8 K prod_id [7:0] $end
+$var wire 1 ? trap $end
+$var wire 1 L wrstb $end
+$var wire 1 8 sdo_enb $end
+$var wire 1 M rdstb $end
+$var wire 8 N odata [7:0] $end
+$var wire 8 O idata [7:0] $end
+$var wire 8 P iaddr [7:0] $end
+$var wire 1 9 SDO $end
+$var reg 1 6 irq $end
+$var reg 1 3 pll_bypass $end
+$var reg 1 2 pll_dco_ena $end
+$var reg 5 Q pll_div [4:0] $end
+$var reg 3 R pll_sel [2:0] $end
+$var reg 26 S pll_trim [25:0] $end
+$var reg 1 . reg_ena $end
+$var reg 1 7 reset $end
+$var reg 1 - xtal_ena $end
+$scope module U1 $end
+$var wire 1 : CSB $end
+$var wire 1 < SCK $end
+$var wire 1 = SDI $end
+$var wire 8 T idata [7:0] $end
+$var wire 8 U odata [7:0] $end
+$var wire 8 V oaddr [7:0] $end
+$var wire 1 9 SDO $end
+$var reg 8 W addr [7:0] $end
+$var reg 3 X count [2:0] $end
+$var reg 3 Y fixed [2:0] $end
+$var reg 8 Z ldata [7:0] $end
+$var reg 7 [ predata [6:0] $end
+$var reg 1 M rdstb $end
+$var reg 1 \ readmode $end
+$var reg 1 8 sdoenb $end
+$var reg 2 ] state [1:0] $end
+$var reg 1 ^ writemode $end
+$var reg 1 L wrstb $end
+$upscope $end
+$upscope $end
+$scope module uut $end
+$var wire 4 _ iomem_we [3:0] $end
+$var wire 1 3 pll_bypass $end
+$var wire 1 ` resetn $end
+$var wire 8 a spi_ro_config [7:0] $end
+$var wire 4 b spi_ro_mask_rev [3:0] $end
+$var wire 12 c spi_ro_mfgr_id [11:0] $end
+$var wire 1 2 spi_ro_pll_dco_ena $end
+$var wire 5 d spi_ro_pll_div [4:0] $end
+$var wire 3 e spi_ro_pll_sel [2:0] $end
+$var wire 26 f spi_ro_pll_trim [25:0] $end
+$var wire 8 g spi_ro_prod_id [7:0] $end
+$var wire 1 . spi_ro_reg_ena $end
+$var wire 1 - spi_ro_xtal_ena $end
+$var wire 1 h valid $end
+$var wire 1 , wb_ack_o $end
+$var wire 32 i wb_adr_i [31:0] $end
+$var wire 1 A wb_clk_i $end
+$var wire 1 B wb_cyc_i $end
+$var wire 32 j wb_dat_i [31:0] $end
+$var wire 1 D wb_rst_i $end
+$var wire 4 k wb_sel_i [3:0] $end
+$var wire 1 F wb_stb_i $end
+$var wire 1 G wb_we_i $end
+$var wire 32 l wb_dat_o [31:0] $end
+$var wire 1 m ready $end
+$scope module spi_sysctrl $end
+$var wire 1 A clk $end
+$var wire 32 n iomem_addr [31:0] $end
+$var wire 1 h iomem_valid $end
+$var wire 32 o iomem_wdata [31:0] $end
+$var wire 4 p iomem_wstrb [3:0] $end
+$var wire 1 3 pll_bypass $end
+$var wire 1 ` resetn $end
+$var wire 8 q spi_ro_config [7:0] $end
+$var wire 4 r spi_ro_mask_rev [3:0] $end
+$var wire 12 s spi_ro_mfgr_id [11:0] $end
+$var wire 1 2 spi_ro_pll_dco_ena $end
+$var wire 5 t spi_ro_pll_div [4:0] $end
+$var wire 3 u spi_ro_pll_sel [2:0] $end
+$var wire 26 v spi_ro_pll_trim [25:0] $end
+$var wire 8 w spi_ro_prod_id [7:0] $end
+$var wire 1 . spi_ro_reg_ena $end
+$var wire 1 - spi_ro_xtal_ena $end
+$var wire 1 x spi_prod_sel $end
+$var wire 1 y spi_mfgr_sel $end
+$var wire 1 z spi_maskrev_sel $end
+$var wire 1 { spi_ena_sel $end
+$var wire 1 | spi_cfg_sel $end
+$var wire 1 } pll_cfg_sel $end
+$var wire 1 ~ pll_bypass_sel $end
+$var reg 32 !" iomem_rdata [31:0] $end
+$var reg 1 m iomem_ready $end
+$upscope $end
+$upscope $end
+$scope task read $end
+$var reg 33 "" addr [32:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+bx ""
+bx !"
+0~
+0}
+1|
+0{
+0z
+0y
+0x
+b101 w
+b11111111111110111111111111 v
+b0 u
+b100 t
+b10001010110 s
+bx r
+bz q
+b0 p
+b0 o
+b0 n
+xm
+bx l
+b0 k
+b0 j
+b0 i
+0h
+b101 g
+b11111111111110111111111111 f
+b0 e
+b100 d
+b10001010110 c
+bx b
+bz a
+0`
+b0 _
+0^
+b0 ]
+0\
+b0 [
+b0 Z
+b0 Y
+b0 X
+b0 W
+b0 V
+b0 U
+b0 T
+b11111111111110111111111111 S
+b0 R
+b100 Q
+b0 P
+b0 O
+b0 N
+0M
+0L
+b101 K
+b10001010110 J
+bx I
+bx H
+0G
+0F
+b0 E
+1D
+b0 C
+0B
+0A
+b0 @
+x?
+bx >
+0=
+0<
+0;
+1:
+09
+18
+07
+06
+15
+bx 4
+13
+12
+b100 1
+b0 0
+b11111111111110111111111111 /
+1.
+1-
+x,
+bx +
+b101 *
+b10001010110 )
+bz (
+b101110000000000000000000010000 '
+b101110000000000000000000001000 &
+b101110000000000000000000011000 %
+b101110000000000000000000001100 $
+b101110000000000000000000010100 #
+b101110000000000000000000000100 "
+b101110000000000000000000000000 !
+$end
+#1000
+0,
+0m
+1A
+#2000
+05
+1`
+0A
+1;
+0D
+#3000
+1A
+#4000
+0A
+b101110000000000000000000010100 ""
+b1111 4
+b1111 H
+b1111 b
+b1111 r
+b1111 >
+b1111 I
+#5000
+0|
+1z
+1h
+b101110000000000000000000010100 @
+b101110000000000000000000010100 i
+b101110000000000000000000010100 n
+1B
+1F
+1A
+#6000
+0A
+#7000
+b1111 +
+b1111 l
+b1111 !"
+1,
+1m
+1A
+#8000
+0A
+#9000
+0h
+b101110000000000000000000001100 ""
+0F
+0B
+0,
+0m
+1A
+#10000
+0A
+#11000
+1y
+0z
+1h
+b101110000000000000000000001100 @
+b101110000000000000000000001100 i
+b101110000000000000000000001100 n
+1B
+1F
+1A
+#12000
+0A
+#13000
+b10001010110 +
+b10001010110 l
+b10001010110 !"
+1,
+1m
+1A
+#14000
+0A
+#15000
+0h
+b101110000000000000000000010000 ""
+0F
+0B
+0,
+0m
+1A
+#16000
+0A
+#17000
+0y
+1x
+1h
+b101110000000000000000000010000 @
+b101110000000000000000000010000 i
+b101110000000000000000000010000 n
+1B
+1F
+1A
+#18000
+0A
+#19000
+b101 +
+b101 l
+b101 !"
+1,
+1m
+1A
+#20000
+0A
+#21000
+0h
+b101110000000000000000000011000 ""
+0F
+0B
+0,
+0m
+1A
+#22000
+0A
+#23000
+0x
+1~
+1h
+b101110000000000000000000011000 @
+b101110000000000000000000011000 i
+b101110000000000000000000011000 n
+1B
+1F
+1A
+#24000
+0A
+#25000
+b1 +
+b1 l
+b1 !"
+1,
+1m
+1A
+#26000
+0A
+#27000
+0h
+b101110000000000000000000001000 ""
+0F
+0B
+0,
+0m
+1A
+#28000
+0A
+#29000
+1}
+0~
+1h
+b101110000000000000000000001000 @
+b101110000000000000000000001000 i
+b101110000000000000000000001000 n
+1B
+1F
+1A
+#30000
+0A
+#31000
+b111111111111101111111111111 +
+b111111111111101111111111111 l
+b111111111111101111111111111 !"
+1,
+1m
+1A
+#32000
+0A
+#33000
+0h
+b101110000000000000000000000100 ""
+0F
+0B
+0,
+0m
+1A
+#34000
+0A
+#35000
+1{
+0}
+1h
+b101110000000000000000000000100 @
+b101110000000000000000000000100 i
+b101110000000000000000000000100 n
+1B
+1F
+1A
+#36000
+0A
+#37000
+b10000011 +
+b10000011 l
+b10000011 !"
+1,
+1m
+1A
+#38000
+0A
+#39000
+0h
+0F
+0B
+0,
+0m
+1A
diff --git a/verilog/dv/wb/spimemio_wb/Makefile b/verilog/dv/wb/spimemio_wb/Makefile
new file mode 100644
index 0000000..075241d
--- /dev/null
+++ b/verilog/dv/wb/spimemio_wb/Makefile
@@ -0,0 +1,18 @@
+.SUFFIXES:
+
+PATTERN = spimemio_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog -I ../ -I ../../  -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+
diff --git a/verilog/dv/wb/spimemio_wb/flash.hex b/verilog/dv/wb/spimemio_wb/flash.hex
new file mode 100644
index 0000000..23bd76d
--- /dev/null
+++ b/verilog/dv/wb/spimemio_wb/flash.hex
@@ -0,0 +1,6 @@
+@10000000
+a1
+b1
+c1
+d1
+f1
\ No newline at end of file
diff --git a/verilog/dv/wb/spimemio_wb/spimemio_wb_tb.v b/verilog/dv/wb/spimemio_wb/spimemio_wb_tb.v
new file mode 100644
index 0000000..b75e6fc
--- /dev/null
+++ b/verilog/dv/wb/spimemio_wb/spimemio_wb_tb.v
@@ -0,0 +1,217 @@
+
+
+`timescale 1 ns / 1 ps
+
+`define FLASH_BASE  32'h 1000_000
+
+`include "spimemio.v"
+// `include "spiflash.v"
+
+module spimemio_wb_tb;
+
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    reg wb_flash_stb_i;
+	reg wb_cfg_stb_i;
+	reg wb_cyc_i;
+	reg wb_we_i;
+	reg [3:0]  wb_sel_i;
+	reg [31:0] wb_adr_i;
+	reg [31:0] wb_dat_i;
+
+	wire wb_flash_ack_o;
+    wire wb_cfg_ack_o;
+	wire [31:0] wb_flash_dat_o;
+	wire [31:0] wb_cfg_dat_o;
+
+    wire flash_csb;
+    wire flash_clk;
+
+    wire flash_io0_oeb;
+    wire flash_io1_oeb;
+    wire flash_io2_oeb;
+    wire flash_io3_oeb;
+
+    wire flash_io0_di = 1'b 1;
+    wire flash_io1_di = 1'b 1;
+    wire flash_io2_di = 1'b 1;
+    wire flash_io3_di = 1'b 1;
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_flash_stb_i = 0;  
+        wb_cfg_stb_i = 0; 
+        wb_cyc_i = 0;   
+        wb_we_i  = 0;
+        wb_sel_i = 0;    
+        wb_adr_i = 0;  
+        wb_dat_i = 0;  
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    spimemio_wb uut(
+        .wb_clk_i(wb_clk_i),
+	    .wb_rst_i(wb_rst_i),
+        
+        .wb_flash_stb_i(wb_flash_stb_i),
+	    .wb_cfg_stb_i(wb_cfg_stb_i),
+	    .wb_cyc_i(wb_cyc_i),
+    	.wb_we_i(wb_we_i),
+	    .wb_sel_i(wb_sel_i),
+	    .wb_adr_i(wb_adr_i), 
+	    .wb_dat_i(wb_dat_i),
+	    .wb_flash_ack_o(wb_flash_ack_o),
+        .wb_cfg_ack_o(wb_cfg_ack_o),
+	    .wb_flash_dat_o(wb_flash_dat_o),
+	    .wb_cfg_dat_o(wb_cfg_dat_o),
+
+        .flash_clk(flash_clk),
+        .flash_csb(flash_csb),
+
+        .flash_io0_oeb(flash_io0_oeb),
+        .flash_io1_oeb(flash_io1_oeb),
+        .flash_io2_oeb(flash_io2_oeb),
+        .flash_io3_oeb(flash_io3_oeb),
+
+        .flash_io0_di(flash_io0_di),
+        .flash_io1_di(flash_io1_di),
+	    .flash_io2_di(flash_io2_di),
+	    .flash_io3_di(flash_io3_di)       
+    );
+
+    initial begin
+        $dumpfile("spimemio_wb_tb.vcd");
+        $dumpvars(0, spimemio_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test spimmemio Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+        
+    wire [31:0] cfgreg_data;
+    assign cfgreg_data = {
+        1'b 1,
+        8'b 0,
+        3'b 111,
+        4'b 1010,
+        4'b 0,             // make sure is it tied to zero in the module itself
+        {~flash_io3_oeb, ~flash_io2_oeb, ~flash_io1_oeb, ~flash_io0_oeb},
+        2'b 0,
+        flash_csb,
+        flash_clk,
+        {flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di}
+    };
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0; 
+        #2;
+
+        // Read from flash
+        for (i = `FLASH_BASE; i < `FLASH_BASE + 100 ; i = i + 4) begin
+            read(i, 1, 0);
+            if (wb_flash_dat_o !== 32'hFFFF_FFFF) begin
+                $display("%c[1;31m",27);
+                $display("Expected %0b, but Got %0b ",  32'hFFFF_FFFF, wb_flash_dat_o);
+                $display("Monitor: Wishbone spimemio Failed");
+            	$display("%c[0m",27);
+                $finish;
+            end
+            #2;
+        end 
+
+        #6;
+        // Write to Configuration register
+        write(cfgreg_data, 0);
+        #2;
+        read(0, 0, 1);
+        if (wb_cfg_dat_o !== cfgreg_data) begin
+            $display("%c[1;31m",27);
+            $display("Expected %0b, but Got %0b ",  cfgreg_data, wb_cfg_dat_o);
+            $display("Monitor: Wishbone spimemio Failed");
+            $display("%c[0m",27);
+            $finish;
+        end
+        
+        $display("Success!");
+        $finish;
+    end
+    
+    task write;
+        input [32:0] data;
+        input [31:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_cfg_stb_i = 1'b 1;
+                wb_flash_stb_i = 1'b 0;
+                wb_cyc_i = 1'b 1;
+                wb_sel_i = 4'b 1111; // complete word
+                wb_we_i = 1'b 1;     // write enable
+                wb_adr_i = addr;
+                wb_dat_i = data;
+            end
+
+            wait_ack();
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        input flash_stb;
+        input cfg_stb;
+        begin 
+            wb_flash_stb_i = flash_stb;
+            wb_cfg_stb_i = cfg_stb;
+
+            wb_cyc_i = 1'b 1;
+            wb_adr_i = addr;
+            wb_dat_i = 24;
+            wb_sel_i = 4'b 1111; // complete word
+            wb_we_i = 1'b 0;     // read
+            $display("Initiated Read transaction...");
+            wait_ack();
+        end
+    endtask
+
+    task wait_ack;
+        // Wait for an ACK
+        if (wb_cfg_stb_i == 1) begin
+            @(posedge wb_cfg_ack_o) begin
+                #2;  // To end the transaction on the falling edge of ack 
+                wb_cyc_i = 1'b 0;
+                wb_cfg_stb_i = 1'b 0;
+                $display("Monitor: Received an ACK from slave");
+            end
+        end
+        else begin
+            @(posedge wb_flash_ack_o) begin
+                #2;  // To end the transaction on the falling edge of ack 
+                wb_cyc_i = 1'b 0;
+                wb_flash_stb_i = 1'b 0;
+                $display("Monitor: Received an ACK from slave");
+            end
+        end
+    endtask
+
+    // spiflash #(
+	// 	.FILENAME("flash.hex")
+	// ) spiflash (
+	// 	.csb(flash_csb),
+	// 	.clk(flash_clk),
+	// 	.io0(flash_io0),
+	// 	.io1(flash_io1),
+	// 	.io2(flash_io2),
+	// 	.io3(flash_io3)
+	// );
+    
+endmodule
\ No newline at end of file
diff --git a/verilog/dv/wb/sysctrl_wb/Makefile b/verilog/dv/wb/sysctrl_wb/Makefile
new file mode 100644
index 0000000..e1b0978
--- /dev/null
+++ b/verilog/dv/wb/sysctrl_wb/Makefile
@@ -0,0 +1,18 @@
+.SUFFIXES:
+
+PATTERN = sysctrl_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog  -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+
diff --git a/verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.v
new file mode 100644
index 0000000..e0ec433
--- /dev/null
+++ b/verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.v
@@ -0,0 +1,222 @@
+
+`timescale 1 ns / 1 ps
+
+`include "sysctrl.v"
+
+module sysctrl_wb_tb;
+
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    reg wb_stb_i;
+    reg wb_cyc_i;
+	reg wb_we_i;
+	reg [3:0] wb_sel_i;
+	reg [31:0] wb_dat_i;
+	reg [31:0] wb_adr_i;
+
+	wire wb_ack_o;
+	wire [31:0] wb_dat_o;
+    
+    reg overtemp;
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_stb_i = 0; 
+        wb_cyc_i = 0;  
+        wb_sel_i = 0;  
+        wb_we_i  = 0;  
+        wb_dat_i = 0; 
+        wb_adr_i = 0; 
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+    
+    initial begin
+        $dumpfile("sysctrl_wb_tb.vcd");
+        $dumpvars(0, sysctrl_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test System Control Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+    
+    // System Control Default Register Addresses 
+    wire [31:0] osc_ena_adr   = uut.BASE_ADR | uut.OSC_ENA;  
+    wire [31:0] osc_out_adr   = uut.BASE_ADR | uut.OSC_OUT;
+    wire [31:0] xtal_out_adr  = uut.BASE_ADR | uut.XTAL_OUT;
+    wire [31:0] pll_out_adr   = uut.BASE_ADR | uut.PLL_OUT;
+    wire [31:0] trap_out_adr  = uut.BASE_ADR | uut.TRAP_OUT;
+    wire [31:0] irq7_src_adr  = uut.BASE_ADR | uut.IRQ7_SRC;
+    wire [31:0] irq8_src_adr  = uut.BASE_ADR | uut.IRQ8_SRC;
+    wire [31:0] overtemp_adr  = uut.BASE_ADR | uut.OVERTEMP_DATA;
+    wire [31:0] overtemp_ena_adr  = uut.BASE_ADR | uut.OVERTEMP_ENA;
+    wire [31:0] ovetemp_out_adr   = uut.BASE_ADR | uut.OVERTEMP_OUT;
+
+    reg rcosc_ena;
+    reg [1:0] rcosc_output_dest;
+    reg [1:0] xtal_output_dest;
+    reg [1:0] pll_output_dest;
+    reg [1:0] trap_output_dest;
+    reg [1:0] irq_7_inputsrc;
+    reg [1:0] irq_8_inputsrc;
+    reg overtemp_ena;
+    reg [1:0] overtemp_dest;
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0;
+        #2;
+        
+        overtemp  = 1'b1;
+        rcosc_ena = 1'b1;
+        rcosc_output_dest = 2'b10;
+        xtal_output_dest  = 2'b01;
+        pll_output_dest   = 2'b11;
+        trap_output_dest  = 2'b10;
+        irq_7_inputsrc    = 2'b01;
+        irq_8_inputsrc    = 2'b11;
+        overtemp_ena  = 1'b1;
+        overtemp_dest = 1'b1;
+
+        // Write to System Control Registers (except overtemp; read-only)
+        write(osc_ena_adr, rcosc_ena);
+        write(osc_out_adr, rcosc_output_dest);
+        write(xtal_out_adr, xtal_output_dest);
+        write(pll_out_adr, pll_output_dest);
+        write(trap_out_adr, trap_output_dest);
+        write(irq7_src_adr, irq_7_inputsrc);
+        write(irq8_src_adr, irq_8_inputsrc);
+        write(overtemp_ena_adr, overtemp_ena);
+        write(ovetemp_out_adr, overtemp_dest);
+        
+        #2;
+        // Read System Control Registers
+        read(overtemp_adr);
+        if (wb_dat_o !== overtemp) begin
+            $display("Error reading from overtemp reg");
+            $finish;
+        end
+
+        read(osc_ena_adr);
+        if (wb_dat_o !== rcosc_ena) begin
+            $display("Error reading oscillator enable register.");
+            $finish;
+        end
+
+        read(osc_out_adr);
+        if (wb_dat_o !== rcosc_output_dest) begin
+            $display("Error reading oscillator output destination register.");
+            $finish;
+        end
+        
+        read(xtal_out_adr);
+        if (wb_dat_o !== xtal_output_dest) begin
+            $display("Error reading XTAL output destination register.");
+            $finish;
+        end
+
+        read(pll_out_adr);
+        if (wb_dat_o !== pll_output_dest) begin
+            $display("Error reading PLL output destination register.");
+            $finish;
+        end
+
+        read(trap_out_adr);
+        if (wb_dat_o !== trap_output_dest) begin
+            $display("Error reading trap output destination register.");
+            $finish;
+        end
+
+        read(irq7_src_adr);
+        if (wb_dat_o !== irq_7_inputsrc) begin
+            $display("Error reading IRQ7 input source register.");
+            $finish;
+        end
+
+        read(irq8_src_adr);
+        if (wb_dat_o !== irq_8_inputsrc) begin
+            $display("Error reading IRQ7 input source register.");
+            $finish;
+        end
+
+        read(overtemp_ena_adr);
+        if (wb_dat_o !== overtemp_ena) begin
+            $display("Error reading over-temperature enable register.");
+            $finish;
+        end
+
+        read(ovetemp_out_adr);
+        if (wb_dat_o !== overtemp_dest) begin
+            $display("Error reading over-temperature output destination register.");
+            $finish;
+        end
+
+        $display("Success!");
+        $finish;
+    end
+    
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF; 
+                wb_we_i = 1;     
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Monitor: Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Monitor: Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Monitor: Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Monitor: Read Cycle Ended.");
+        end
+    endtask
+
+    sysctrl_wb uut(
+        .wb_clk_i(wb_clk_i),
+	    .wb_rst_i(wb_rst_i),
+        .wb_stb_i(wb_stb_i),
+	    .wb_cyc_i(wb_cyc_i),
+	    .wb_sel_i(wb_sel_i),
+	    .wb_we_i(wb_we_i),
+	    .wb_dat_i(wb_dat_i),
+	    .wb_adr_i(wb_adr_i), 
+        .wb_ack_o(wb_ack_o),
+	    .wb_dat_o(wb_dat_o),
+        .overtemp(overtemp)
+    );
+    
+endmodule
diff --git a/verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.vcd b/verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.vcd
new file mode 100644
index 0000000..31cad7c
--- /dev/null
+++ b/verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.vcd
@@ -0,0 +1,828 @@
+$date
+	Fri Aug 21 14:21:19 2020
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module sysctrl_wb_tb $end
+$var wire 32 ! irq7_src_adr [31:0] $end
+$var wire 32 " irq8_src_adr [31:0] $end
+$var wire 32 # osc_ena_adr [31:0] $end
+$var wire 32 $ osc_out_adr [31:0] $end
+$var wire 32 % overtemp_adr [31:0] $end
+$var wire 32 & overtemp_ena_adr [31:0] $end
+$var wire 32 ' ovetemp_out_adr [31:0] $end
+$var wire 32 ( pll_out_adr [31:0] $end
+$var wire 32 ) trap_out_adr [31:0] $end
+$var wire 32 * xtal_out_adr [31:0] $end
+$var wire 32 + wb_dat_o [31:0] $end
+$var wire 1 , wb_ack_o $end
+$var reg 2 - irq_7_inputsrc [1:0] $end
+$var reg 2 . irq_8_inputsrc [1:0] $end
+$var reg 1 / overtemp $end
+$var reg 2 0 overtemp_dest [1:0] $end
+$var reg 1 1 overtemp_ena $end
+$var reg 2 2 pll_output_dest [1:0] $end
+$var reg 1 3 rcosc_ena $end
+$var reg 2 4 rcosc_output_dest [1:0] $end
+$var reg 2 5 trap_output_dest [1:0] $end
+$var reg 32 6 wb_adr_i [31:0] $end
+$var reg 1 7 wb_clk_i $end
+$var reg 1 8 wb_cyc_i $end
+$var reg 32 9 wb_dat_i [31:0] $end
+$var reg 1 : wb_rst_i $end
+$var reg 4 ; wb_sel_i [3:0] $end
+$var reg 1 < wb_stb_i $end
+$var reg 1 = wb_we_i $end
+$var reg 2 > xtal_output_dest [1:0] $end
+$scope module uut $end
+$var wire 4 ? iomem_we [3:0] $end
+$var wire 1 / overtemp $end
+$var wire 1 @ resetn $end
+$var wire 1 A valid $end
+$var wire 1 , wb_ack_o $end
+$var wire 32 B wb_adr_i [31:0] $end
+$var wire 1 7 wb_clk_i $end
+$var wire 1 8 wb_cyc_i $end
+$var wire 32 C wb_dat_i [31:0] $end
+$var wire 1 : wb_rst_i $end
+$var wire 4 D wb_sel_i [3:0] $end
+$var wire 1 < wb_stb_i $end
+$var wire 1 = wb_we_i $end
+$var wire 2 E xtal_output_dest [1:0] $end
+$var wire 32 F wb_dat_o [31:0] $end
+$var wire 2 G trap_output_dest [1:0] $end
+$var wire 1 H ready $end
+$var wire 2 I rcosc_output_dest [1:0] $end
+$var wire 1 J rcosc_ena $end
+$var wire 2 K pll_output_dest [1:0] $end
+$var wire 1 L overtemp_ena $end
+$var wire 2 M overtemp_dest [1:0] $end
+$var wire 2 N irq_8_inputsrc [1:0] $end
+$var wire 2 O irq_7_inputsrc [1:0] $end
+$scope module sysctrl $end
+$var wire 1 7 clk $end
+$var wire 32 P iomem_addr [31:0] $end
+$var wire 1 A iomem_valid $end
+$var wire 32 Q iomem_wdata [31:0] $end
+$var wire 4 R iomem_wstrb [3:0] $end
+$var wire 1 / overtemp $end
+$var wire 1 @ resetn $end
+$var wire 1 S xtal_out_sel $end
+$var wire 1 T trap_out_sel $end
+$var wire 1 U pll_out_sel $end
+$var wire 1 V overtemp_sel $end
+$var wire 1 W overtemp_ena_sel $end
+$var wire 1 X overtemp_dest_sel $end
+$var wire 1 Y osc_out_sel $end
+$var wire 1 Z osc_ena_sel $end
+$var wire 1 [ irq8_sel $end
+$var wire 1 \ irq7_sel $end
+$var reg 32 ] iomem_rdata [31:0] $end
+$var reg 1 H iomem_ready $end
+$var reg 2 ^ irq_7_inputsrc [1:0] $end
+$var reg 2 _ irq_8_inputsrc [1:0] $end
+$var reg 2 ` overtemp_dest [1:0] $end
+$var reg 1 L overtemp_ena $end
+$var reg 2 a pll_output_dest [1:0] $end
+$var reg 1 J rcosc_ena $end
+$var reg 2 b rcosc_output_dest [1:0] $end
+$var reg 2 c trap_output_dest [1:0] $end
+$var reg 2 d xtal_output_dest [1:0] $end
+$upscope $end
+$upscope $end
+$scope task read $end
+$var reg 33 e addr [32:0] $end
+$upscope $end
+$scope task write $end
+$var reg 33 f addr [32:0] $end
+$var reg 33 g data [32:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+bx g
+bx f
+bx e
+bx d
+bx c
+bx b
+bx a
+bx `
+bx _
+bx ^
+bx ]
+0\
+0[
+1Z
+0Y
+0X
+0W
+0V
+0U
+0T
+0S
+b0 R
+b0 Q
+b0 P
+bx O
+bx N
+bx M
+xL
+bx K
+xJ
+bx I
+xH
+bx G
+bx F
+bx E
+b0 D
+b0 C
+b0 B
+0A
+0@
+b0 ?
+bx >
+0=
+0<
+b0 ;
+1:
+b0 9
+08
+07
+b0 6
+bx 5
+bx 4
+x3
+bx 2
+x1
+bx 0
+x/
+bx .
+bx -
+x,
+bx +
+b101111000000000000000000001000 *
+b101111000000000000000000010000 )
+b101111000000000000000000001100 (
+b101111000000000000000000100100 '
+b101111000000000000000000011100 &
+b101111000000000000000000100000 %
+b101111000000000000000000000100 $
+b101111000000000000000000000000 #
+b101111000000000000000000011000 "
+b101111000000000000000000010100 !
+$end
+#1000
+0L
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+b0 `
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+b0 O
+b0 ^
+b0 G
+b0 c
+b0 E
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+b101111000000000000000000000000 6
+b101111000000000000000000000000 B
+b101111000000000000000000000000 P
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+b1111 ;
+b1111 D
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+b0 ]
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+07
+#9000
+0A
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+b101111000000000000000000000100 P
+18
+1<
+17
+#12000
+07
+#13000
+b10 I
+b10 b
+1,
+1H
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+07
+#15000
+0A
+b1 g
+b101111000000000000000000001000 f
+0<
+08
+0,
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+17
+#16000
+07
+#17000
+0Y
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+b1 C
+b1 Q
+b101111000000000000000000001000 6
+b101111000000000000000000001000 B
+b101111000000000000000000001000 P
+18
+1<
+17
+#18000
+07
+#19000
+b1 E
+b1 d
+1,
+1H
+17
+#20000
+07
+#21000
+0A
+b11 g
+b101111000000000000000000001100 f
+0<
+08
+0,
+0H
+17
+#22000
+07
+#23000
+1U
+0S
+1A
+b11 9
+b11 C
+b11 Q
+b101111000000000000000000001100 6
+b101111000000000000000000001100 B
+b101111000000000000000000001100 P
+18
+1<
+17
+#24000
+07
+#25000
+b11 K
+b11 a
+1,
+1H
+17
+#26000
+07
+#27000
+0A
+b10 g
+b101111000000000000000000010000 f
+0<
+08
+0,
+0H
+17
+#28000
+07
+#29000
+0U
+1T
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+b10 Q
+b101111000000000000000000010000 6
+b101111000000000000000000010000 B
+b101111000000000000000000010000 P
+18
+1<
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+#30000
+07
+#31000
+b10 G
+b10 c
+1,
+1H
+17
+#32000
+07
+#33000
+0A
+b1 g
+b101111000000000000000000010100 f
+0<
+08
+0,
+0H
+17
+#34000
+07
+#35000
+0T
+1\
+1A
+b1 9
+b1 C
+b1 Q
+b101111000000000000000000010100 6
+b101111000000000000000000010100 B
+b101111000000000000000000010100 P
+18
+1<
+17
+#36000
+07
+#37000
+b1 O
+b1 ^
+1,
+1H
+17
+#38000
+07
+#39000
+0A
+b11 g
+b101111000000000000000000011000 f
+0<
+08
+0,
+0H
+17
+#40000
+07
+#41000
+0\
+1[
+1A
+b11 9
+b11 C
+b11 Q
+b101111000000000000000000011000 6
+b101111000000000000000000011000 B
+b101111000000000000000000011000 P
+18
+1<
+17
+#42000
+07
+#43000
+b11 N
+b11 _
+1,
+1H
+17
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diff --git a/verilog/dv/wb/uart_wb/Makefile b/verilog/dv/wb/uart_wb/Makefile
new file mode 100644
index 0000000..a37bd82
--- /dev/null
+++ b/verilog/dv/wb/uart_wb/Makefile
@@ -0,0 +1,17 @@
+.SUFFIXES:
+
+PATTERN = uart_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog -I .. -I ../../ -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/wb/uart_wb/uart_wb_tb.v b/verilog/dv/wb/uart_wb/uart_wb_tb.v
new file mode 100644
index 0000000..6063060
--- /dev/null
+++ b/verilog/dv/wb/uart_wb/uart_wb_tb.v
@@ -0,0 +1,149 @@
+
+
+`timescale 1 ns / 1 ps
+
+`include "simpleuart.v"
+
+module uart_wb_tb;
+    
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    reg wb_stb_i;
+	reg wb_cyc_i;
+	reg wb_we_i;
+	reg [3:0] wb_sel_i;
+	reg [31:0] wb_adr_i;
+	reg [31:0] wb_dat_i;
+
+	wire wb_ack_o;
+	wire [31:0] wb_dat_o;
+  
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_stb_i = 0; 
+        wb_we_i  = 0;  
+        wb_cyc_i = 0;  
+        wb_adr_i = 0; 
+        wb_dat_i = 0; 
+        wb_sel_i = 0;  
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    initial begin
+        $dumpfile("uart_wb_tb.vcd");
+        $dumpvars(0, uart_wb_tb);
+        repeat (500) begin
+            repeat (10000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display("Monitor: Timeout, Test UART Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    wire [31:0] div_reg_addr = uut.BASE_ADR | uut.CLK_DIV;
+    wire [31:0] div_reg_data = 32'h FFFF_FFFF;
+    
+    wire [31:0] dat_reg_addr = uut.BASE_ADR | uut.DATA;
+    wire [31:0] dat_reg_data = 32'h FFFF_FFFF;
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0; 
+        #2;
+
+        // Write to div register
+        write(div_reg_addr, div_reg_data);
+        #2;
+        read(div_reg_addr);
+        if (wb_dat_o !== div_reg_data) begin
+            $display("%c[1;31m",27);
+            $display("Expected %0b, but Got %0b ", div_reg_data, wb_dat_o);
+            $display("Monitor: Wishbone UART Failed");
+            $display("%c[0m",27);
+            $finish;
+        end
+        #6;
+
+        // Write Operation: writes to data register
+        write(dat_reg_addr, dat_reg_data);
+        #2;
+        read(dat_reg_addr);
+        if (wb_dat_o !== dat_reg_data) begin
+            $display("%c[1;31m",27);
+            $display("Expected %0b, but Got %0b ", dat_reg_data, wb_dat_o);
+            $display("Monitor: Wishbone UART Failed");
+            $display("%c[0m",27);
+            $finish;
+        end
+        $display("Success!");
+        $finish;
+    end
+    
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF; 
+                wb_we_i = 1;     
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            #2;
+            wb_we_i = 0;     
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            #2;
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            #2;
+            // wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Read Cycle Ended.");
+        end
+    endtask
+    
+    simpleuart_wb uut (
+		.wb_clk_i(wb_clk_i),
+		.wb_rst_i(wb_rst_i),
+    	.wb_stb_i(wb_stb_i),
+    	.wb_cyc_i(wb_cyc_i),
+    	.wb_sel_i(wb_sel_i),
+    	.wb_we_i(wb_we_i),
+        .wb_adr_i(wb_adr_i),      
+	    .wb_dat_i(wb_dat_i),
+	    .wb_ack_o(wb_ack_o),
+	    .wb_dat_o(wb_dat_o),
+        .ser_tx(tbuart_rx),
+		.ser_rx(ser_rx)
+	);
+
+endmodule
\ No newline at end of file