)]}'
{
  "commit": "e4bec999f226a5299064b2fe96aa40ac122ee78e",
  "tree": "425b1c971b7d4414bd3515a36075d57dc12d8c1d",
  "parents": [
    "06ea56ff358130843dbb90b87a8e483d1db0e5b5"
  ],
  "author": {
    "name": "Arya Reais-Parsi",
    "email": "himself@aryaparsi.com",
    "time": "Fri Dec 18 13:56:31 2020 -0800"
  },
  "committer": {
    "name": "Arya Reais-Parsi",
    "email": "himself@aryaparsi.com",
    "time": "Fri Dec 18 13:56:31 2020 -0800"
  },
  "message": "add rtl sources, dv\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "a5e9d36e8c0d35bf9fa4e1566b50f2b46b32e811",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/fpga_250/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "4852f2c9ff33f17bb849cef68c88263a15baf3f2",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/fpga_250/README.md"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "85b0b1db2f9442f97adc19e2c2a267fa44759eeb",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/fpga_250/basic_config/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "534977423a10bc33fb58ec87c79075b676f91700",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/fpga_250/basic_config/basic_config.bits"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "9dd63a3b8caedb9a59278129d6b32aa91ffc7ac9",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/fpga_250/basic_config/basic_config.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "6e6dc5d6fe9f4edc2f00241ae419300be8e06f52",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/fpga_250/basic_config/basic_config_tb.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3279887b4e780c88c19ac9160c98276aca3df2c6",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/fpga_250/primitive_config/fpga250_tb.v"
    },
    {
      "type": "modify",
      "old_id": "ff068f053f2b1935affa6081b39594627605b860",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_project_wrapper.v",
      "new_id": "ab4e979c4d27b1008e3d9db113b80b2c89f6e042",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project_wrapper.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "031c35aa47b2712b91cd6a46f7c91b97b46e8c29",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/baked_clb_switch_box.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b3f725a4afcfd453740d391e65d98bce9a0b9efb",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/baked_connection_block.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "4d9145dccf1a0e65c630e5d82a3662df9bb8ce17",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/baked_connection_block_east.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "4d01d48ff4fd3e89e778496a670cfd731f1630a8",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/baked_connection_block_north.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "38e5aa76ffc631bda645fa55a91b275919945a6d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/baked_slicel.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "7541d367d1e0572f853aebb0591d83afaacc38c8",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/block_config_latches.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "6216bb429281dd6ecf6b4c77f11aa84381b248e9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/carry_chain.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "90889695adfc7167eaf23ad1c10f844125d9f186",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/clb_switch_box.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "84066811ad0fdc990ae1d6a31dbe7b0a40337c49",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/clb_tile.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "2e5525927955af86c6eaad960897d83b15ded260",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/config_latch.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8202ae73f3dcf3d0f8a28e5e498a99fdca1db7d4",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/config_tile.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "178931b53e5f786091f438f43a94dd6e07dc5120",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/connection_block.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "66fa39eaf36098147cefec20a2512217c9cecf68",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/fpga.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "95f9f2449d516973fc2be7910da840dd37121427",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/lut.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "94749db8d3fc68fd9de8c07ee28f67f012544d49",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/lut_sXX_softcode.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "aca46d71b48c303801e5a375b6efc76b1e85cbfe",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/mux_f_slice.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "c40849da0760476004b45d2ff666d13094180ee5",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/shift_chain.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8e5ee80abfb55cc68561403374e0fd1083db6a67",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/slicel.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e7648753e622608075a6af66028a213a8639040f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/switch_box_element_two.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "623db3abbd8d3c52b5131709edace5bcb79747c0",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/transmission_gate.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "0e6494a19bc628143ad8f2e930443b2a0c450156",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/transmission_gate_cell.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "636ae48b6c63d07cd3ed470f0e24023b0b30b3ba",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/transmission_gate_oneway.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e62e490c2731cadffbeff68d1dc49bcbf63ae14d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/universal_switch_box.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "ecacb476c33addd1ce5b84e6f2b65eb79788efe9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/wishbone_configuratorinator.v"
    },
    {
      "type": "modify",
      "old_id": "47d92f4d6bb0cdbdca2175f28fa88f12fd574096",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "dc960393af5f052c402a045d46f6c740c2b0ed70",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}