)]}'
{
  "commit": "d9b784dcc546decd8bb1d84dc06be06d7e2bd913",
  "tree": "52d2d0e7c8dc9f4c6d6e6c944061549fcaff5372",
  "parents": [
    "d13e475798b9851e2cbd10faf899df96419c7313"
  ],
  "author": {
    "name": "nqdtan",
    "email": "tan.nqd@gmail.com",
    "time": "Sat Dec 19 16:47:20 2020 -0800"
  },
  "committer": {
    "name": "nqdtan",
    "email": "tan.nqd@gmail.com",
    "time": "Sat Dec 19 16:47:20 2020 -0800"
  },
  "message": "pass power pins when simulation; use VCS for now :/\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7a5f7dd68ce858b1bc1c1e164a00f431b1a99b2d",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/fpga_250/standalone_test/bitstream.txt",
      "new_id": "8c07512ace4f023b6be8a60926a2c185ba30fdf4",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/fpga_250/standalone_test/bitstream.txt"
    },
    {
      "type": "modify",
      "old_id": "c17f38b95d0ec97fe8ebd21afe2cab8ed2d83a91",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/fpga_250/standalone_test/comb_output.txt",
      "new_id": "e57b5e50895f564246b64f2bc65b90137baf9a94",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/fpga_250/standalone_test/comb_output.txt"
    },
    {
      "type": "modify",
      "old_id": "960b8a72ae1fecd8b05853f97ce32adef4929a53",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/fpga_250/standalone_test/sync_output.txt",
      "new_id": "f1092e777f669793e93c8333d4df80062056b39b",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/fpga_250/standalone_test/sync_output.txt"
    },
    {
      "type": "modify",
      "old_id": "cf3209183a208c1357bb2f66f9cf81b7a0162f49",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/fpga_250/standalone_test/user_project_wrapper_tb.v",
      "new_id": "72d44843d08e62198fbca2699ea75f325ea82f4d",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/fpga_250/standalone_test/user_project_wrapper_tb.v"
    },
    {
      "type": "modify",
      "old_id": "7541d367d1e0572f853aebb0591d83afaacc38c8",
      "old_mode": 33188,
      "old_path": "verilog/rtl/fpga250/block_config_latches.v",
      "new_id": "90869383f13eeb58aae7c60f995219cec6d63017",
      "new_mode": 33188,
      "new_path": "verilog/rtl/fpga250/block_config_latches.v"
    }
  ]
}
