)]}'
{
  "commit": "8115320f43c8069cbf52bdc6deb34b44bf520a5b",
  "tree": "0df07176e0d6816dc4216f84bf779eb5c252084c",
  "parents": [
    "856b092898d166106f28702cf979f7fa74cb3c47"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Oct 09 19:57:04 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Oct 09 19:57:04 2020 -0400"
  },
  "message": "Modified code to let SPI master control the housekeeping SPI through\na configuration bit setting in the SPI master.  Revised the \"sysctrl\"\ntestbench to work with the SPI master controlling the housekeeping\nSPI.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "70b5b4a34bf093c09e07b20d033cee35466b0deb",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c",
      "new_id": "3d2cefde527a995e94499321f219c5b8705b52ec",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c"
    },
    {
      "type": "modify",
      "old_id": "c1a1e2ada35147020fd69ad0b634d0601ad8dcb5",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v",
      "new_id": "adcbb48c5cbef35aebf3c6857231574b708b4825",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v"
    },
    {
      "type": "modify",
      "old_id": "8ae1b815338919ec1be8423aa9aa3605c5d292c6",
      "old_mode": 33188,
      "old_path": "verilog/rtl/housekeeping_spi.v",
      "new_id": "42677d4f6dd436ff31909154b4fe6294794dfc6f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/housekeeping_spi.v"
    },
    {
      "type": "modify",
      "old_id": "49b29cdf90ff87c1c91bcde80ff3ab554e643a8a",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_core.v",
      "new_id": "297b76ae8d9039359c52026fe8553016b93dd21a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_core.v"
    },
    {
      "type": "modify",
      "old_id": "e5375ffdf4976945100679e7db059f5ec636eb19",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_soc.v",
      "new_id": "5f1050d40ca9ed4069bb8e4cdafc7f36428b748f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_soc.v"
    },
    {
      "type": "modify",
      "old_id": "a2a33b671edb95ac3f1aedf57c2fce2a460eba68",
      "old_mode": 33261,
      "old_path": "verilog/rtl/simple_spi_master.v",
      "new_id": "447f0f11aa5397624c5a8bde5500150a3463a4a3",
      "new_mode": 33261,
      "new_path": "verilog/rtl/simple_spi_master.v"
    }
  ]
}