diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v
index 8ae1b81..42677d4 100644
--- a/verilog/rtl/housekeeping_spi.v
+++ b/verilog/rtl/housekeeping_spi.v
@@ -32,7 +32,7 @@
 // Caravel defined registers:
 // Register 0:  SPI status and control (unused & reserved)
 // Register 1 and 2:  Manufacturer ID (0x0456) (readonly)
-// Register 3:  Product ID (= 2) (readonly)
+// Register 3:  Product ID (= 16) (readonly)
 // Register 4-7: Mask revision (readonly) --- Externally programmed
 //	with via programming.  Via programmed with a script to match
 //	each customer ID.
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 49b29cd..297b76a 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -77,6 +77,7 @@
     	wire ext_clk_sel;
     	wire pll_clk;
     	wire ext_reset;
+	wire hk_connect;
 
 	caravel_clkrst clkrst(
 	`ifdef LVS
@@ -165,6 +166,8 @@
 		.pass_thru_mgmt_sck(pass_thru_mgmt_sck),
 		.pass_thru_mgmt_sdi(pass_thru_mgmt_sdi),
 		.pass_thru_mgmt_sdo(pass_thru_mgmt_sdo),
+		// SPI master->slave direct connection
+		.hk_connect(hk_connect),
 		// Logic Analyzer
 		.la_input(la_input),
 		.la_output(la_output),
@@ -229,9 +232,9 @@
 		.vss(vss),
 	    `endif
 	    .RSTB(porb),
-	    .SCK(mgmt_in_data[4]),
-	    .SDI(mgmt_in_data[2]),
-	    .CSB(mgmt_in_data[3]),
+	    .SCK((hk_connect) ? mgmt_out_data[4] : mgmt_in_data[4]),
+	    .SDI((hk_connect) ? mgmt_out_data[2] : mgmt_in_data[2]),
+	    .CSB((hk_connect) ? mgmt_out_data[3] : mgmt_in_data[3]),
 	    .SDO(sdo_out),
 	    .sdo_enb(sdo_outenb),
 	    .pll_dco_ena(spi_pll_dco_ena),
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index e5375ff..5f1050d 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -122,6 +122,9 @@
     input  pass_thru_mgmt_sdi,
     output pass_thru_mgmt_sdo,
 
+    // SPI master->slave direct link
+    output hk_connect,
+
     // WB MI A (Mega project)
     input mprj_ack_i,
     input [31:0] mprj_dat_i,
@@ -481,6 +484,7 @@
         .wb_ack_o(spi_master_ack_o),
         .wb_dat_o(spi_master_dat_o),
 
+	.hk_connect(hk_connect),
         .csb(mgmt_out_pre[3]),
         .sck(mgmt_out_pre[4]),
         .sdi(mgmt_in_data[1]),
diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
index a2a33b6..447f0f1 100755
--- a/verilog/rtl/simple_spi_master.v
+++ b/verilog/rtl/simple_spi_master.v
@@ -46,6 +46,9 @@
 // irqena:
 //     0 = disable interrupt
 //     1 = enable interrupt
+// hkconn:
+//     0 = housekeeping SPI disconnected
+//     1 = housekeeping SPI connected (when SPI master enabled)
 // prescaler: count (in master clock cycles) of 1/2 SCK cycle.
 //
 // reg_dat_we:
@@ -78,6 +81,7 @@
     output wb_ack_o,
     output [31:0] wb_dat_o,
 
+    output	 hk_connect,	// Connect to housekeeping SPI
     input 	 sdi,	 // SPI input
     output 	 csb,	 // SPI chip select
     output 	 sck,	 // SPI clock
@@ -118,6 +122,7 @@
     	.reg_dat_do(simple_spi_master_reg_dat_do),
     	.reg_dat_wait(reg_dat_wait),
 
+	.hk_connect(hk_connect),	// Attach to housekeeping SPI slave
     	.sdi(sdi),	 // SPI input
     	.csb(csb),	 // SPI chip select
     	.sck(sck),	 // SPI clock
@@ -142,6 +147,7 @@
     output	  irq_out,
     output	  err_out,
 
+    output	 hk_connect,	// Connect to housekeeping SPI
     input 	 sdi,	 // SPI input
     output 	 csb,	 // SPI chip select
     output 	 sck,	 // SPI clock
@@ -171,12 +177,14 @@
     reg	   stream;
     reg	   mode;
     reg	   enable;
+    reg	   hkconn;
  
     wire	  csb;
     wire	  irq_out;
     wire	  sck;
     wire	  sdo;
     wire	  sdoenb;
+    wire	  hk_connect;
 
     // Define behavior for inverted SCK and inverted CSB
     assign    	  csb = (enable == 1'b0) ? 1'bz : (invcsb) ? ~icsb : icsb;
@@ -188,9 +196,11 @@
     assign	  sdo = (enable == 1'b0) ? 1'bz : isdo;
 
     assign	  irq_out = irqena & done;
+    assign	  hk_connect = (enable == 1'b1) ? hkconn : 1'b0;
 
     // Read configuration and data registers
-    assign reg_cfg_do = {17'd0, irqena, enable, stream, mode, invsck, invcsb, mlb, prescaler};
+    assign reg_cfg_do = {16'd0, hkconn, irqena, enable, stream, mode,
+			 invsck, invcsb, mlb, prescaler};
     assign reg_dat_wait = ~done;
     assign reg_dat_do = done ? rreg : ~0;
 
@@ -205,6 +215,7 @@
 	    irqena <= 1'b0;
 	    stream <= 1'b0;
 	    mode <= 1'b0;
+	    hkconn <= 1'b0;
         end else begin
             if (reg_cfg_we[0]) prescaler <= reg_cfg_di[7:0];
             if (reg_cfg_we[1]) begin
@@ -215,6 +226,7 @@
 	        stream <= reg_cfg_di[12];
 	        enable <= reg_cfg_di[13];
 	        irqena <= reg_cfg_di[14];
+	        hkconn <= reg_cfg_di[15];
 	    end //reg_cfg_we[1]
         end //resetn
     end //always