diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index 3a16147..4f6891e 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -80,18 +80,15 @@
 );
 
 `ifndef USE_OPENRAM
-    reg [31:0] rdata;
-    reg [31:0] mem [0:WORDS-1];
-
-    always @(posedge clk) begin
-        if (ena == 1'b1) begin
-            rdata <= mem[addr];
-            if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
-            if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
-            if (wen[2]) mem[addr][23:16] <= wdata[23:16];
-            if (wen[3]) mem[addr][31:24] <= wdata[31:24];
-        end
-    end
+    DFFRAM SRAM (
+        .CLK(clk),
+        .WE(wen),
+        .EN(ena),
+        .Di(wdata),
+        .Do(rdata),
+        // 8-bit address if using the default custom DFF RAM
+        .A(addr)
+    );
 `else
     
     /* Using Port 0 Only - Size: 1KB, 256x32 bits */
@@ -108,4 +105,4 @@
 
 `endif
 
-endmodule
\ No newline at end of file
+endmodule