)]}'
{
  "commit": "545efbf6d18f34c3864ae8c31d4dbf1443179f97",
  "tree": "5f8705aad3cbb2be1b00866ca4d990fb63c4927c",
  "parents": [
    "cb7132a9273be296eb3dd9ee2181e299273bef77"
  ],
  "author": {
    "name": "nqdtan",
    "email": "tan.nqd@gmail.com",
    "time": "Mon Dec 21 16:48:13 2020 -0800"
  },
  "committer": {
    "name": "nqdtan",
    "email": "tan.nqd@gmail.com",
    "time": "Mon Dec 21 16:48:13 2020 -0800"
  },
  "message": "forgot to enable output in user_project\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "dc960393af5f052c402a045d46f6c740c2b0ed70",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "1b8c80060b87baae42f71507d4da83a1584f7aef",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}