)]}'
{
  "commit": "406d37f79d5ea22de4b73d998525ccdd72fca9f1",
  "tree": "910aede28610700cf6d460db044bb15471e580cf",
  "parents": [
    "907394669505129b4a7baf4fb8236313fc552af3"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Oct 09 22:21:30 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Oct 09 22:21:30 2020 -0400"
  },
  "message": "Solved the trap issue by not driving the PLL clock so fast (not sure why\nthat happens in a behavioral simulation, though).  PLL still needs glitch-\nfree switching and needs to be able to run the PLL and let it settle before\nswitching the core clock.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ac0c3756d70971d98cea10f7becfb11875faea83",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/pll/pll.c",
      "new_id": "dd8e0d6bc3bafc19bd846b5451b60b3cb42cfb35",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/pll/pll.c"
    }
  ]
}