diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index fa85ee2..12a597e 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -117,8 +117,8 @@
 
     output flash_csb,
     output flash_clk,
-    output flash_io0,
-    output flash_io1
+    inout flash_io0,
+    inout flash_io1
 );
 
     //------------------------------------------------------------
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index dff9c0f..8241d99 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -125,7 +125,7 @@
 	assign sdo_out = (sdo_oenb_state == 1'b0) ? mgmt_out_data[1] : sdo_out_pre;
 	assign jtag_out = (jtag_oenb_state == 1'b0) ? mgmt_out_data[0] : jtag_out_pre;
 
-	caravel_clocking clocking(
+	caravel_clocking clocking_inst (
 	`ifdef USE_POWER_PINS
 		.vdd1v8(VPWR),
 		.vss(VGND),
diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v
index 23d9cf6..cb11a7a 100644
--- a/verilog/rtl/mgmt_protect_hv.v
+++ b/verilog/rtl/mgmt_protect_hv.v
@@ -45,8 +45,10 @@
 `ifdef USE_POWER_PINS
     // This is to emulate the substrate shorting grounds together for LVS
     // purposes
-    assign vssa2 = vssa1;
-    assign vssa1 = vssd;
+    //assign vssa2 = vssa1;
+    //assign vssa1 = vssd;
+    tran(vssa2, vssa1);
+    tran(vssa1, vssd);
 `endif
 
     // Logic high in the VDDA (3.3V) domains
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 17a73f4..d55e8db 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -479,6 +479,8 @@
         .ser_rx(mgmt_in_data[5])
     );
 
+    wire [`MPRJ_IO_PADS-1:0] mgmt_out_pre;
+
     // Wishbone SPI master
     wire spi_master_stb_i;
     wire spi_master_ack_o;
@@ -503,6 +505,7 @@
         .wb_ack_o(spi_master_ack_o),
         .wb_dat_o(spi_master_dat_o),
 
+
 	.hk_connect(hk_connect),
         .csb(mgmt_out_pre[3]),
         .sck(mgmt_out_pre[4]),
@@ -693,7 +696,6 @@
     wire mprj_ctrl_stb_i;
     wire mprj_ctrl_ack_o;
     wire [31:0] mprj_ctrl_dat_o;
-    wire [`MPRJ_IO_PADS-1:0] mgmt_out_pre;
 
     // Bits assigned to specific functions as outputs prevent the
     // mprj GPIO-as-output from applying data when that function
diff --git a/verilog/rtl/wb_intercon.v b/verilog/rtl/wb_intercon.v
index 7ebce83..2013eb8 100644
--- a/verilog/rtl/wb_intercon.v
+++ b/verilog/rtl/wb_intercon.v
@@ -17,7 +17,23 @@
 module wb_intercon #(
     parameter DW = 32,          // Data Width
     parameter AW = 32,          // Address Width
-    parameter NS = 6           // Number of Slaves
+    parameter NS = 6,           // Number of Slaves
+    parameter [NS*AW-1:0] ADR_MASK = {      // Page & Sub-page bits
+        {8'hFF, {24{1'b0}} },
+        {8'hFF, {24{1'b0}} },
+        {8'hFF, {24{1'b0}} },
+        {8'hFF, {24{1'b0}} },
+        {8'hFF, {24{1'b0}} },
+        {8'hFF, {24{1'b0}} }
+    },
+    parameter [NS*AW-1:0] SLAVE_ADR = {
+        { 32'h2800_0000 },    // Flash Configuration Register
+        { 32'h2200_0000 },    // System Control
+        { 32'h2100_0000 },    // GPIOs
+        { 32'h2000_0000 },    // UART 
+        { 32'h1000_0000 },    // Flash 
+        { 32'h0000_0000 }     // RAM
+    }
 ) (
     // Master Interface
     input [AW-1:0] wbm_adr_i,
@@ -31,23 +47,7 @@
     input [NS-1:0] wbs_ack_i,
     output [NS-1:0] wbs_stb_o
 );
-    parameter [NS*AW-1:0] ADR_MASK = {      // Page & Sub-page bits
-        {8'hFF, {24{1'b0}} },
-        {8'hFF, {24{1'b0}} },
-        {8'hFF, {24{1'b0}} },
-        {8'hFF, {24{1'b0}} },
-        {8'hFF, {24{1'b0}} },
-        {8'hFF, {24{1'b0}} }
-    };
-    parameter [NS*AW-1:0] SLAVE_ADR = {
-        { 32'h2800_0000 },    // Flash Configuration Register
-        { 32'h2200_0000 },    // System Control
-        { 32'h2100_0000 },    // GPIOs
-        { 32'h2000_0000 },    // UART 
-        { 32'h1000_0000 },    // Flash 
-        { 32'h0000_0000 }     // RAM
-    };
-    
+
     wire [NS-1: 0] slave_sel;
 
     // Address decoder