diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index 559151d..ac5dfdf 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -112,12 +112,12 @@
 #define GPIO_MODE_MGMT_STD_INPUT_NOPULL    0x0403
 #define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN  0x0803
 #define GPIO_MODE_MGMT_STD_INPUT_PULLUP	   0x0c03
-#define GPIO_MODE_MGMT_STD_OUTPUT	   0x1801
+#define GPIO_MODE_MGMT_STD_OUTPUT	   0x1809
 
 #define GPIO_MODE_USER_STD_INPUT_NOPULL	   0x0402
 #define GPIO_MODE_USER_STD_INPUT_PULLDOWN  0x0802
 #define GPIO_MODE_USER_STD_INPUT_PULLUP	   0x0c02
-#define GPIO_MODE_USER_STD_OUTPUT	   0x1800
+#define GPIO_MODE_USER_STD_OUTPUT	   0x1808
 
 // --------------------------------------------------------
 #endif
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio.c b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
index 9053551..d58c176 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
@@ -91,7 +91,7 @@
 	reg_mprj_data = 0xab000000;
 
 	while (1){
-		int x = reg_mprj_data & 0xff0000;
+		int x = (reg_mprj_data & 0xff0000) >> 16;
 		reg_mprj_data = (x+1) << 24;
 	}
 }
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index 56781da..615e4d1 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -64,7 +64,6 @@
 	wire flash_io1;
 
 	reg RSTB;
-	reg CSB, SCK, SDI;
 	wire SDO;
 
 	// Transactor
@@ -100,9 +99,6 @@
 	end
 
 	initial begin
-		CSB <= 1'b1;
-		SCK <= 1'b0;
-		SDI <= 1'b0;
 		RSTB <= 1'b0;
 		
 		#1000;
@@ -139,7 +135,7 @@
 	wire [11:0] noconnect;
 	wire [2:0] spi_sigs;
 
-	assign spi_sigs = 3'b010;
+	assign spi_sigs = 3'b010;	// Set SCK, CSB, and SDI
 
 	caravel uut (
 		.vdd3v3	  (VDD3V3),
@@ -148,7 +144,6 @@
 		.clock	  (clock),
 		.gpio     (gpio),
 		.mprj_io  ({checkbits, noconnect[11:1],
-				// SCK, CSB, SDI, SDO, noconnect[0]}),
 				spi_sigs, SDO, noconnect[0]}),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart.hex b/verilog/dv/caravel/mgmt_soc/uart/uart.hex
deleted file mode 100755
index bb0c729..0000000
--- a/verilog/dv/caravel/mgmt_soc/uart/uart.hex
+++ /dev/null
@@ -1,36 +0,0 @@
-@00000000
-93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00 
-13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00 
-13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00 
-13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00 
-13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 
-13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 
-13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 
-13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 45 1B 
-93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 
-11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00 
-63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 11 22 
-01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00 
-A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00 
-23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3 
-F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F 
-00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01 
-93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00 
-93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00 
-23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC 
-FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08 
-A3 81 62 00 82 80 01 00 00 00 01 11 06 CE 22 CC 
-00 10 AA 87 A3 07 F4 FE 03 47 F4 FE A9 47 63 14 
-F7 00 35 45 DD 37 B7 07 00 20 91 07 03 47 F4 FE 
-98 C3 01 00 F2 40 62 44 05 61 82 80 01 11 06 CE 
-22 CC 00 10 23 26 A4 FE 19 A8 83 27 C4 FE 13 87 
-17 00 23 26 E4 FE 83 C7 07 00 3E 85 7D 37 83 27 
-C4 FE 83 C7 07 00 F5 F3 01 00 F2 40 62 44 05 61 
-82 80 41 11 06 C6 22 C4 00 08 B7 07 00 20 13 07 
-10 27 98 C3 B7 07 00 21 23 A0 07 00 B7 07 00 21 
-91 07 23 A0 07 00 B7 07 00 21 05 47 98 C3 B7 07 
-00 10 13 85 47 20 59 3F B7 07 00 10 13 85 87 20 
-71 37 B7 07 00 21 09 47 98 C3 01 00 B2 40 22 44 
-41 01 82 80 0A 00 00 00 4D 6F 6E 69 74 6F 72 3A 
-20 54 65 73 74 20 55 41 52 54 20 28 52 54 4C 29 
-20 70 61 73 73 65 64 0A 0A 00 00 00 
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index c51bef1..58dd692 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -47,6 +47,7 @@
 `include "chip_io.v"
 `include "user_id_programming.v"
 `include "gpio_control_block.v"
+`include "simple_por.v"
 
 `ifdef USE_OPENRAM
     `include "sram_1rw1r_32_8192_8_sky130.v"
@@ -175,6 +176,9 @@
     wire porb_h;
     wire porb_l;
 
+    wire rstb_h;
+    wire rstb_l;
+
     // To be considered:  Master hold signal on all user pads (?)
     // For now, set holdh_n to 1 (NOTE:  This is in the 3.3V domain)
     // and setting enh to porb_h.
@@ -196,6 +200,7 @@
 	.flash_io1(flash_io1),
 	// SoC Core Interface
 	.porb_h(porb_h),
+	.resetb_core_h(rstb_h),
 	.clock_core(clock_core),
 	.gpio_out_core(gpio_out_core),
 	.gpio_in_core(gpio_in_core),
@@ -297,7 +302,8 @@
 		.flash_io1_do(flash_io1_do_core),
 		.flash_io0_di(flash_io0_di_core),
 		.flash_io1_di(flash_io1_di_core),
-		// Power-on Reset
+		// Master Reset
+		.resetb(rstb_l),
 		.porb(porb_l),
 		// Clocks and reset
 		.clock(clock_core),
@@ -452,7 +458,7 @@
     	.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):2])
     );
 
-    sky130_fd_sc_hvl__lsbufhv2lv levelshift (
+    sky130_fd_sc_hvl__lsbufhv2lv porb_level (
 	`ifdef LVS
 		.vpwr(vdd3v3),
 		.vpb(vdd3v3),
@@ -470,4 +476,24 @@
 	.mask_rev(mask_rev)
     );
 
+    // Power-on-reset circuit
+    simple_por por (
+		.vdd3v3(vdd3v3),
+		.vss(vss),
+		.porb_h(porb_h)
+    );
+
+    // XRES (chip input pin reset) reset level converter
+    sky130_fd_sc_hvl__lsbufhv2lv rstb_level (
+	`ifdef LVS
+		.vpwr(vdd3v3),
+		.vpb(vdd3v3),
+		.lvpwr(vdd1v8),
+		.vnb(vss),
+		.vgnd(vss),
+	`endif
+		.A(rstb_h),
+		.X(rstb_l)
+    );
+
 endmodule
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index dc46ebf..d34cfec 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -11,7 +11,8 @@
 	inout  flash_io0,
 	inout  flash_io1,
 	// Chip Core Interface
-	output porb_h,
+	input  porb_h,
+	output resetb_core_h,
 	output clock_core,
 	input  gpio_out_core,
     	output gpio_in_core,
@@ -169,7 +170,7 @@
 		.tie_hi_esd(),
 		.tie_lo_esd(),
 		.pad_a_esd_h(xresloop),
-		.xres_h_n(porb_h),
+		.xres_h_n(resetb_core_h),
 		.disable_pullup_h(vss),	    // 0 = enable pull-up on reset pad
 		.enable_h(vdd3v3),	    // Power-on-reset to the power-on-reset input??
 		.en_vddio_sig_h(vss),	    // No idea.
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index bd52027..e6b837b 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -25,6 +25,7 @@
 	input flash_io0_di,
 	input flash_io1_di,
 	// Master reset
+	input resetb,
 	input porb,
 	// Clocking
 	input clock,
@@ -79,7 +80,7 @@
 		.ext_clk_sel(ext_clk_sel),
 		.ext_clk(clock),		// Should be better handled. . .
 		.pll_clk(pll_clk),
-		.resetb(porb), 
+		.resetb(resetb), 
 		.ext_reset(ext_reset),
 		.core_clk(core_clk),
 		.resetb_sync(core_rstn)
@@ -203,7 +204,7 @@
 		.vdd(vdd1v8),
 		.vss(vss),
 	    `endif
-		.resetb(porb),
+		.resetb(resetb),
 		.extclk_sel(ext_clk_sel),
 		.osc(clock),
 		.clockc(pll_clk),
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
new file mode 100644
index 0000000..4b92a55
--- /dev/null
+++ b/verilog/rtl/simple_por.v
@@ -0,0 +1,52 @@
+module simple_por(
+    input vdd3v3,
+    input vss,
+    output porb_h
+);
+
+    wire mid, porb_h;
+    reg inode;
+
+    // This is a behavioral model!  Actual circuit is a resitor dumping
+    // current (slowly) from vdd3v3 onto a capacitor, and this fed into
+    // two schmitt triggers for strong hysteresis/glitch tolerance.
+
+    initial begin
+	inode <= 1'b0;
+    end 
+
+    // Emulate current source on capacitor as a 500ns delay either up or
+    // down.
+
+    always @(posedge vdd3v3) begin
+	#500 inode <= 1'b1;
+    end
+    always @(negedge vdd3v3) begin
+	#500 inode <= 1'b0;
+    end
+
+    // Instantiate two shmitt trigger buffers in series
+
+    sky130_fd_sc_hvl__schmittbuf hystbuf1 (
+`ifdef LVS
+	.VPWR(vdd3v3),
+	.VGND(vss),
+	.VPB(vdd3v3),
+	.VNB(vss),
+`endif
+	.A(inode),
+	.X(mid)
+    );
+
+    sky130_fd_sc_hvl__schmittbuf hystbuf2 (
+`ifdef LVS
+	.VPWR(vdd3v3),
+	.VGND(vss),
+	.VPB(vdd3v3),
+	.VNB(vss),
+`endif
+	.A(mid),
+	.X(porb_h)
+    );
+
+endmodule