diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..e3dd6ee
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,7 @@
+[submodule "cargo/wb2axip"]
+	path = cargo/wb2axip
+	url = https://github.com/milovanovic/wb2axip.git
+[submodule "cargo/lis"]
+	path = cargo/lis
+	url = https://github.com/milovanovic/lis.git
+	branch = lisTest
diff --git a/cargo/Makefile b/cargo/Makefile
new file mode 100644
index 0000000..9e9b17e
--- /dev/null
+++ b/cargo/Makefile
@@ -0,0 +1,29 @@
+LIS_PATH = ./lis
+TOP_TEST_PATH = ./top/dv/LISTest/lis
+
+SIZE?=24
+export LIS_SIZE=$(SIZE)
+
+move_user_proj_example:
+	mv ../verilog/rtl/user_proj_example.v ./user_proj_example.v
+
+move_back_user_proj_example:
+	mv ./user_proj_example.v ../verilog/rtl/user_proj_example.v 
+	
+verilog_lis:
+	cd $(LIS_PATH); sbt -J-Xmx2048m -J-XX:MaxMetaspaceSize=2048m "runMain lis.LISTestApp"; cd -;
+
+test_lis:
+	cd $(LIS_PATH);sbt -J-Xmx2048m -J-XX:MaxMetaspaceSize=2048m "testOnly lis.LISTestSpec"; cd -;
+
+.PHONY: test_top
+test_top:
+	make move_user_proj_example
+	make verilog_lis
+	make test_lis
+	cd $(TOP_TEST_PATH); make all; cd -;
+	make move_back_user_proj_example
+
+clean_top:
+	cd $(TOP_TEST_PATH); make clean; cd -;
+	
diff --git a/cargo/README.md b/cargo/README.md
new file mode 100644
index 0000000..62554d1
--- /dev/null
+++ b/cargo/README.md
@@ -0,0 +1,17 @@
+
+LINSORTER - LinearINsertion SORTER 
+=======================================================
+
+Block diagram of the LinearINsertion SORTER is given below and detailed explanation of the each block is given inside submodules `lis` and `wb2axip`.
+
+![Global block scheme of the LINSORTER](./doc/images/LinearSorters.svg)
+
+This directory contains following submodules and directories:
+
+* Submodule `lis` -  contains a linear insertion sorter (LIS) generator written in [Chisel ](http://www.chisel-lang.org) hardware design language. It comprises description of three types of the linear insertion sorter, parameter definition, setup explanation and many other useful information related to blocks that are depicted at presented global block scheme.
+* Submodule  `wb2axip` - contains wishbone to AXI4 bridge. Current submodule is forked version of the [ZipCPU/wb2axip](https://github.com/ZipCPU/wb2axip). While all blocks inside LINSORTER use AXI4 memory mapped bus, this bridge was necessary to attach so that correct connection between processor and linear insertion sorters is established.
+* `doc` - contains global block scheme of the LINSORTER in svg and png format.
+* `top/dv/LISTest` - contains verilog testbenches mostly, together with .c files.
+* `top/rtl/LISTest` - contains `user_proj_example.v`.
+* Makefile - have targets for verilog generation (module LISTest) and for running scala tests described  inside `lis` submodule.
+
diff --git a/cargo/doc/images/LinearSorters.png b/cargo/doc/images/LinearSorters.png
new file mode 100644
index 0000000..eacb0e7
--- /dev/null
+++ b/cargo/doc/images/LinearSorters.png
Binary files differ
diff --git a/cargo/doc/images/LinearSorters.svg b/cargo/doc/images/LinearSorters.svg
new file mode 100644
index 0000000..c8785e1
--- /dev/null
+++ b/cargo/doc/images/LinearSorters.svg
@@ -0,0 +1,3 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
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width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 93px; height: 1px; padding-top: 108px; margin-left: 260px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#666666"><b>AXI4</b></font></div></div></div></foreignObject><text x="260" y="112" fill="#000000" font-family="Helvetica" font-size="12px">AXI4</text></switch></g><rect x="258" y="119" width="165" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 163px; height: 1px; padding-top: 129px; margin-left: 260px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#666666"><b>AXI4-Stream 32b<br /></b></font></div></div></div></foreignObject><text x="260" y="133" fill="#000000" font-family="Helvetica" font-size="12px">AXI4-Stream 32b&#xa;</text></switch></g><path d="M 175 175 L 237.53 175" fill="none" stroke="#6c8ebf" stroke-width="4" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 245.53 175 L 237.53 177.67 L 237.53 172.33 Z" fill="#6c8ebf" stroke="#6c8ebf" stroke-width="4" stroke-miterlimit="10" pointer-events="all"/><rect x="258" y="143" width="165" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 163px; height: 1px; padding-top: 153px; margin-left: 260px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#666666"><b>AXI4-Stream 8b<br /></b></font></div></div></div></foreignObject><text x="260" y="157" fill="#000000" font-family="Helvetica" font-size="12px">AXI4-Stream 8b&#xa;</text></switch></g><rect x="258" y="164" width="165" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 163px; height: 1px; padding-top: 174px; margin-left: 260px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#666666"><b>Single line<br /></b></font></div></div></div></foreignObject><text x="260" y="178" fill="#000000" font-family="Helvetica" font-size="12px">Single line&#xa;</text></switch></g><rect x="432" y="49" width="100" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 98px; height: 1px; padding-top: 59px; margin-left: 433px;"><div style="box-sizing: border-box; font-size: 0; text-align: center; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 18px" color="#666666"><b>Blocks:</b></font></div></div></div></foreignObject><text x="482" y="63" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="middle">Blocks:</text></switch></g><rect x="447" y="78" width="338" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 336px; height: 1px; padding-top: 88px; margin-left: 449px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#CC6600">•<font style="font-size: 16px"><sup><span style="font-size: 7px"></span></sup></font></font><font style="font-size: 16px" color="#CC6600"><b> always_ready: ready is <font style="font-size: 16px">always</font> active</b></font></div></div></div></foreignObject><text x="449" y="92" fill="#000000" font-family="Helvetica" font-size="12px">• always_ready: ready is always active</text></switch></g><rect x="447" y="98" width="350" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 348px; height: 1px; padding-top: 108px; margin-left: 449px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#CC6600">•<font style="font-size: 16px"><sup><span style="font-size: 7px"></span></sup></font></font><font size="1" color="#CC6600"><sup><span style="font-size: 7px"></span></sup></font><font style="font-size: 16px" color="#CC6600"><b> all_ones: output is 0xFFFF<br /></b></font></div></div></div></foreignObject><text x="449" y="112" fill="#000000" font-family="Helvetica" font-size="12px">• all_ones: output is 0xFFFF&#xa;</text></switch></g><rect x="447" y="118" width="350" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 348px; height: 1px; padding-top: 128px; margin-left: 449px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#CC6600">•<font style="font-size: 16px"><sup><span style="font-size: 7px"> </span></sup></font></font><font style="font-size: 16px" color="#CC6600"><b>all_zeros: output is 0x0000<br /></b></font></div></div></div></foreignObject><text x="449" y="132" fill="#000000" font-family="Helvetica" font-size="12px">• all_zeros: output is 0x0000&#xa;</text></switch></g></g><switch><g requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"/><a transform="translate(0,-5)" xlink:href="https://desk.draw.io/support/solutions/articles/16000042487" target="_blank"><text text-anchor="middle" font-size="10px" x="50%" y="100%">Viewer does not support full SVG 1.1</text></a></switch></svg>
\ No newline at end of file
diff --git a/cargo/lis b/cargo/lis
new file mode 160000
index 0000000..be02358
--- /dev/null
+++ b/cargo/lis
@@ -0,0 +1 @@
+Subproject commit be02358aad24d7e680b2d769e423504e069a31f8
diff --git a/cargo/top/dv/LISTest/compare.py b/cargo/top/dv/LISTest/compare.py
new file mode 100644
index 0000000..b3bc527
--- /dev/null
+++ b/cargo/top/dv/LISTest/compare.py
@@ -0,0 +1,14 @@
+import sys
+file1 = open(sys.argv[1], 'r')
+file2 = open(sys.argv[2], 'r')
+
+data1 = file1.read()
+data2 = file2.read()
+
+if (data1 == data2):
+    print("Test passed!")
+else:
+    print("Test failed!")
+
+file1.close()
+file2.close()
\ No newline at end of file
diff --git a/cargo/top/dv/LISTest/defs.h b/cargo/top/dv/LISTest/defs.h
new file mode 100644
index 0000000..2402f47
--- /dev/null
+++ b/cargo/top/dv/LISTest/defs.h
@@ -0,0 +1,186 @@
+#ifndef _STRIVE_H_
+#define _STRIVE_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// a pointer to this is a null pointer, but the compiler does not
+// know that because "sram" is a linker symbol from sections.lds.
+extern uint32_t sram;
+
+// Pointer to firmware flash routines
+extern uint32_t flashio_worker_begin;
+extern uint32_t flashio_worker_end;
+
+// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
+#define reg_rw_block0  (*(volatile uint32_t*)0x01000000)
+#define reg_rw_block1  (*(volatile uint32_t*)0x01100000)
+#define reg_ro_block0  (*(volatile uint32_t*)0x02000000)
+
+// UART (0x2000_0000)
+#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_uart_data   (*(volatile uint32_t*)0x20000004)
+#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
+
+// GPIO (0x2100_0000)
+#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
+#define reg_gpio_ena  (*(volatile uint32_t*)0x21000004)
+#define reg_gpio_pu   (*(volatile uint32_t*)0x21000008)
+#define reg_gpio_pd   (*(volatile uint32_t*)0x2100000c)
+
+// Logic Analyzer (0x2200_0000)
+#define reg_la0_data (*(volatile uint32_t*)0x25000000)
+#define reg_la1_data (*(volatile uint32_t*)0x25000004)
+#define reg_la2_data (*(volatile uint32_t*)0x25000008)
+#define reg_la3_data (*(volatile uint32_t*)0x2500000c)
+
+#define reg_la0_ena (*(volatile uint32_t*)0x25000010)
+#define reg_la1_ena (*(volatile uint32_t*)0x25000014)
+#define reg_la2_ena (*(volatile uint32_t*)0x25000018)
+#define reg_la3_ena (*(volatile uint32_t*)0x2500001c)
+
+// User Project Control (0x2300_0000)
+#define reg_mprj_xfer (*(volatile uint32_t*)0x26000000)
+#define reg_mprj_pwr  (*(volatile uint32_t*)0x26000004)
+#define reg_mprj_datal (*(volatile uint32_t*)0x26000008)
+#define reg_mprj_datah (*(volatile uint32_t*)0x2600000c)
+
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x26000020)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000024)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x26000028)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x2600002c)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x26000030)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000034)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x26000038)
+
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x2600003c)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x26000040)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000044)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x26000048)
+
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x2600004c)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x26000050)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000054)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x26000058)
+
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x2600005c)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x26000060)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000064)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x26000068)
+
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x2600006c)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x26000070)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000074)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x26000078)
+
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x2600007c)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x26000080)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000084)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x26000088)
+
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x2600008c)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x26000090)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000094)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x26000098)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x2600009c)
+
+#define reg_mprj_io_32 (*(volatile uint32_t*)0x260000a0)
+#define reg_mprj_io_33 (*(volatile uint32_t*)0x260000a4)
+#define reg_mprj_io_34 (*(volatile uint32_t*)0x260000a8)
+#define reg_mprj_io_35 (*(volatile uint32_t*)0x260000ac)
+#define reg_mprj_io_36 (*(volatile uint32_t*)0x260000b0)
+#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000b4)
+
+// User Project Slaves (0x3000_0000)
+#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+
+// Flash Control SPI Configuration (2D00_0000)
+#define reg_spictrl (*(volatile uint32_t*)0x2d000000)         
+
+// Bit fields for Flash SPI control
+#define FLASH_BITBANG_IO0	0x00000001
+#define FLASH_BITBANG_IO1	0x00000002
+#define FLASH_BITBANG_CLK	0x00000010
+#define FLASH_BITBANG_CSB	0x00000020
+#define FLASH_BITBANG_OEB0	0x00000100
+#define FLASH_BITBANG_OEB1	0x00000200
+#define FLASH_ENABLE		0x80000000
+
+// Counter-Timer 0 Configuration
+#define reg_timer0_config (*(volatile uint32_t*)0x22000000)
+#define reg_timer0_value  (*(volatile uint32_t*)0x22000004)
+#define reg_timer0_data   (*(volatile uint32_t*)0x22000008)
+
+// Counter-Timer 1 Configuration
+#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
+#define reg_timer1_value  (*(volatile uint32_t*)0x23000004)
+#define reg_timer1_data   (*(volatile uint32_t*)0x23000008)
+
+// Bit fields for Counter-timer configuration
+#define TIMER_ENABLE		0x01
+#define TIMER_ONESHOT		0x02
+#define TIMER_UPCOUNT		0x04
+#define TIMER_CHAIN		0x08
+#define TIMER_IRQ_ENABLE	0x10
+
+// SPI Master Configuration
+#define reg_spimaster_config (*(volatile uint32_t*)0x24000000)
+#define reg_spimaster_data   (*(volatile uint32_t*)0x24000004)
+
+// Bit fields for SPI master configuration
+#define SPI_MASTER_DIV_MASK	0x00ff
+#define SPI_MASTER_MLB		0x0100
+#define SPI_MASTER_INV_CSB	0x0200
+#define SPI_MASTER_INV_CLK	0x0400
+#define SPI_MASTER_MODE_1	0x0800
+#define SPI_MASTER_STREAM	0x1000
+#define SPI_MASTER_ENABLE	0x2000
+#define SPI_MASTER_IRQ_ENABLE	0x4000
+#define SPI_HOUSEKEEPING_CONN	0x8000
+
+// System Area (0x2F00_0000)
+#define reg_power_good    (*(volatile uint32_t*)0x2F000000)
+#define reg_clk_out_dest  (*(volatile uint32_t*)0x2F000004)
+#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
+#define reg_irq_source    (*(volatile uint32_t*)0x2F00000C)
+
+// Bit fields for reg_power_good
+#define USER1_VCCD_POWER_GOOD 0x01
+#define USER2_VCCD_POWER_GOOD 0x02
+#define USER1_VDDA_POWER_GOOD 0x04
+#define USER2_VDDA_POWER_GOOD 0x08
+
+// Bit fields for reg_clk_out_dest
+#define CLOCK1_MONITOR 0x01
+#define CLOCK2_MONITOR 0x02
+
+// Bit fields for reg_irq_source
+#define IRQ7_SOURCE 0x01
+#define IRQ8_SOURCE 0x02
+
+// Individual bit fields for the GPIO pad control
+#define MGMT_ENABLE	  0x0001
+#define OUTPUT_DISABLE	  0x0002
+#define HOLD_OVERRIDE	  0x0004
+#define INPUT_DISABLE	  0x0008
+#define MODE_SELECT	  0x0010
+#define ANALOG_ENABLE	  0x0020
+#define ANALOG_SELECT	  0x0040
+#define ANALOG_POLARITY	  0x0080
+#define SLOW_SLEW_MODE	  0x0100
+#define TRIPPOINT_SEL	  0x0200
+#define DIGITAL_MODE_MASK 0x1c00
+
+// Useful GPIO mode values
+#define GPIO_MODE_MGMT_STD_INPUT_NOPULL    0x0403
+#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN  0x0803
+#define GPIO_MODE_MGMT_STD_INPUT_PULLUP	   0x0c03
+#define GPIO_MODE_MGMT_STD_OUTPUT	   0x1809
+
+#define GPIO_MODE_USER_STD_INPUT_NOPULL	   0x0402
+#define GPIO_MODE_USER_STD_INPUT_PULLDOWN  0x0802
+#define GPIO_MODE_USER_STD_INPUT_PULLUP	   0x0c02
+#define GPIO_MODE_USER_STD_OUTPUT	   0x1808
+
+// --------------------------------------------------------
+#endif
diff --git a/cargo/top/dv/LISTest/lis/BIST_LISFIFO_POUT/BIST_LISFIFO_POUT.c b/cargo/top/dv/LISTest/lis/BIST_LISFIFO_POUT/BIST_LISFIFO_POUT.c
new file mode 100644
index 0000000..50be1b1
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/BIST_LISFIFO_POUT/BIST_LISFIFO_POUT.c
@@ -0,0 +1,61 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../../lisDefs.h"
+
+/*
+	LIS Test:
+*/
+
+
+void main()
+{
+	// Configure GPIO pins
+        reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+        reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+
+        reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_6  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+
+        bistAddress_reg(2*BEATBYTES) = 0x1; // configure counter to be active
+        bistAddress_reg(3*BEATBYTES) = 0x1; // configure counter to be up counter
+  
+        lisFIFOMuxAddress0_reg(0) = 0x0;
+        lisFIFOAddress_reg(4*BEATBYTES) = LIS_SIZE/2;
+        lisInputMuxAddress0_reg(BEATBYTES) = 0x0;
+        lisFixedMuxAddress0_reg(BEATBYTES) = 0x0;
+        
+        // configure fixed -> outMux
+        outMuxAddress_reg(0) = 0x0;
+        // configure bist_split -> out_mux
+        outMuxAddress_reg(2*BEATBYTES) = 0x3;
+  
+        // enable bist
+        bistAddress_reg(0) =  0x1; 
+}
\ No newline at end of file
diff --git a/cargo/top/dv/LISTest/lis/BIST_LISFIFO_POUT/BIST_LISFIFO_POUT_tb.v b/cargo/top/dv/LISTest/lis/BIST_LISFIFO_POUT/BIST_LISFIFO_POUT_tb.v
new file mode 100644
index 0000000..efcf439
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/BIST_LISFIFO_POUT/BIST_LISFIFO_POUT_tb.v
@@ -0,0 +1,176 @@
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+
+module BIST_LISFIFO_POUT_tb;
+	// declare file for writing data
+	integer file;
+	
+	// Golden data
+	reg [7:0] goldenData [0:4*`LIS_SIZE-1];
+
+	// clk, rst, power signals
+	reg clock;
+    reg RSTB;
+	reg power1, power2;
+
+	// testbench signals
+    wire 		gpio;
+    wire [37:0] mprj_io;
+
+	// Output stream data wires
+	reg 	    out_ready = 0;
+	wire 	    out_valid;
+	wire  [7:0] out_data;
+	reg   [7:0] out_temp;
+
+	// Input stream data wires
+	wire 	    in_ready;
+	reg 	    in_valid = 0;
+	reg  [7:0]  in_data = 8'h04;
+	reg			in_last = 0;
+
+	reg [15:0] dataCounter = 16'b0;
+
+	// Assign wires
+	assign mprj_io[11]  = out_ready;
+	assign out_valid    = mprj_io[12];
+	assign out_data     = mprj_io[20:13];
+
+	assign in_ready 	= mprj_io[0];
+	assign mprj_io[1]   = in_valid;
+	assign mprj_io[9:2] = in_data[7:0];
+	assign mprj_io[10]  = in_last;
+
+	
+	// toggle clock
+	always #500 clock <= (clock === 1'b0);
+
+	// Read golden data
+	initial $readmemh("./../../../../../../cargo/lis/test_run_dir/LISTest/BIST_LISFIFO_POUT/output.txt", goldenData);
+
+	// open file for writting
+	initial begin
+		$printtimescale(BIST_LISFIFO_POUT_tb);
+		file = $fopen("output.txt","w");
+		if (file) $display("File was opened successfully : %0d", file);
+    	else $display("File was NOT opened successfully : %0d", file);
+	end
+
+	initial begin
+		clock = 0;
+		#500 out_ready = 1'b1; // Set out_ready
+	end
+
+
+	// Check outStream.ready and outStream.valid and collect data
+	always @ (posedge clock) begin
+		if (out_ready == 1'b1 && out_valid == 1'b1) begin
+			$fwriteh(file, "%h\n" ,out_data);
+			if (out_data != goldenData[dataCounter]) begin
+				$display("%c[1;31m",27);
+				$display ("Monitor: Test BIST_LISFIFO_POUT failed!!! Read data was %h, but should be %h.", out_data, goldenData[dataCounter]);
+				$display("%c[0m",27);
+				$fclose(file); 
+				$finish;
+			end
+			dataCounter <= dataCounter + 1'b1;
+		end
+	end
+
+	initial begin
+		$dumpfile("BIST_LISFIFO_POUT.vcd");
+		$dumpvars(0, BIST_LISFIFO_POUT_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Test BIST_LISFIFO_POUT Failed!!! Timeout.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	// Check if enough data was send, and if so terminate test
+	initial begin
+		wait(dataCounter == 16'd 4*`LIS_SIZE);
+		$display("%c[1;32m",27);
+		$display("Monitor: Test BIST_LISFIFO_POUT passed.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#10000;
+		RSTB <= 1'b1;	    // Release reset
+		#20000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("BIST_LISFIFO_POUT.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/cargo/top/dv/LISTest/lis/BIST_LISFIFO_POUT/Makefile b/cargo/top/dv/LISTest/lis/BIST_LISFIFO_POUT/Makefile
new file mode 100644
index 0000000..68a88e7
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/BIST_LISFIFO_POUT/Makefile
@@ -0,0 +1,54 @@
+CARAVEL_PATH = ./../../../../../..
+
+FIRMWARE_PATH = ../..
+RTL_PATH = $(CARAVEL_PATH)/verilog/rtl
+IP_PATH = $(CARAVEL_PATH)/verilog/ip
+BEHAVIOURAL_MODELS = ../../ 
+
+CARGO_PATH   = $(CARAVEL_PATH)/cargo
+WB2AXI_PATH  = $(CARAVEL_PATH)/cargo/wb2axip/rtl
+PROJECT_PATH = $(CARAVEL_PATH)/cargo/lis/rtl/LISTest
+TOP_PATH     = $(CARAVEL_PATH)/cargo/top/rtl/LISTest
+
+GCC_PATH?=$(RISCV32)/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+LIS_SIZE?=24 # Pass fft size to testbench and c code
+
+.SUFFIXES:
+
+PATTERN = BIST_LISFIFO_POUT
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -DSIM -DLIS_SIZE=$(LIS_SIZE) -I $(BEHAVIOURAL_MODELS) \
+	-I $(WB2AXI_PATH)  \
+	-I $(PROJECT_PATH) \
+	-I $(TOP_PATH) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -DLIS_SIZE=$(LIS_SIZE) -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.txt
+
+.PHONY: clean hex all
diff --git a/cargo/top/dv/LISTest/lis/BIST_LISFixed_POUT/BIST_LISFixed_POUT.c b/cargo/top/dv/LISTest/lis/BIST_LISFixed_POUT/BIST_LISFixed_POUT.c
new file mode 100644
index 0000000..d45569a
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/BIST_LISFixed_POUT/BIST_LISFixed_POUT.c
@@ -0,0 +1,62 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../../lisDefs.h"
+
+/*
+	LIS Test:
+*/
+
+
+void main()
+{
+	// Configure GPIO pins
+        reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+        reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+
+        reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_6  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+
+        bistAddress_reg(2*BEATBYTES) = 0x1; // configure counter to be active
+        bistAddress_reg(3*BEATBYTES) = 0x1; // configure counter to be up counter
+  
+        lisFixedMuxAddress0_reg(0) = 0x0;
+        lisFixedAddress_reg(4*BEATBYTES) = LIS_SIZE/2;
+
+        lisFIFOMuxAddress0_reg(BEATBYTES) = 0x0;
+        lisInputMuxAddress0_reg(BEATBYTES) = 0x0;
+        
+        // configure fixed -> outMux
+        outMuxAddress_reg(0) = 0x2;
+        // configure bist_split -> out_mux
+        outMuxAddress_reg(2*BEATBYTES) = 0x3;
+  
+        // enable bist
+        bistAddress_reg(0) =  0x1; 
+}
\ No newline at end of file
diff --git a/cargo/top/dv/LISTest/lis/BIST_LISFixed_POUT/BIST_LISFixed_POUT_tb.v b/cargo/top/dv/LISTest/lis/BIST_LISFixed_POUT/BIST_LISFixed_POUT_tb.v
new file mode 100644
index 0000000..69774d5
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/BIST_LISFixed_POUT/BIST_LISFixed_POUT_tb.v
@@ -0,0 +1,176 @@
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+
+module BIST_LISFixed_POUT_tb;
+	// declare file for writing data
+	integer file;
+	
+	// Golden data
+	reg [7:0] goldenData [0:4*`LIS_SIZE-1];
+
+	// clk, rst, power signals
+	reg clock;
+    reg RSTB;
+	reg power1, power2;
+
+	// testbench signals
+    wire 		gpio;
+    wire [37:0] mprj_io;
+
+	// Output stream data wires
+	reg 	    out_ready = 0;
+	wire 	    out_valid;
+	wire  [7:0] out_data;
+	reg   [7:0] out_temp;
+
+	// Input stream data wires
+	wire 	    in_ready;
+	reg 	    in_valid = 0;
+	reg  [7:0]  in_data = 8'h04;
+	reg			in_last = 0;
+
+	reg [15:0] dataCounter = 16'b0;
+
+	// Assign wires
+	assign mprj_io[11]  = out_ready;
+	assign out_valid    = mprj_io[12];
+	assign out_data     = mprj_io[20:13];
+
+	assign in_ready 	= mprj_io[0];
+	assign mprj_io[1]   = in_valid;
+	assign mprj_io[9:2] = in_data[7:0];
+	assign mprj_io[10]  = in_last;
+
+	
+	// toggle clock
+	always #500 clock <= (clock === 1'b0);
+
+	// Read golden data
+	initial $readmemh("./../../../../../../cargo/lis/test_run_dir/LISTest/BIST_LISFixed_POUT/output.txt", goldenData);
+
+	// open file for writting
+	initial begin
+		$printtimescale(BIST_LISFixed_POUT_tb);
+		file = $fopen("output.txt","w");
+		if (file) $display("File was opened successfully : %0d", file);
+    	else $display("File was NOT opened successfully : %0d", file);
+	end
+
+	initial begin
+		clock = 0;
+		#500 out_ready = 1'b1; // Set out_ready
+	end
+
+
+	// Check outStream.ready and outStream.valid and collect data
+	always @ (posedge clock) begin
+		if (out_ready == 1'b1 && out_valid == 1'b1) begin
+			$fwriteh(file, "%h\n" ,out_data);
+			if (out_data != goldenData[dataCounter]) begin
+				$display("%c[1;31m",27);
+				$display ("Monitor: Test BIST_LISFixed_POUT failed!!! Read data was %h, but should be %h.", out_data, goldenData[dataCounter]);
+				$display("%c[0m",27);
+				$fclose(file); 
+				$finish;
+			end
+			dataCounter <= dataCounter + 1'b1;
+		end
+	end
+
+	initial begin
+		$dumpfile("BIST_LISFixed_POUT.vcd");
+		$dumpvars(0, BIST_LISFixed_POUT_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Test BIST_LISFixed_POUT Failed!!! Timeout.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	// Check if enough data was send, and if so terminate test
+	initial begin
+		wait(dataCounter == 16'd 4*`LIS_SIZE);
+		$display("%c[1;32m",27);
+		$display("Monitor: Test BIST_LISFixed_POUT passed.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#10000;
+		RSTB <= 1'b1;	    // Release reset
+		#20000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("BIST_LISFixed_POUT.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/cargo/top/dv/LISTest/lis/BIST_LISFixed_POUT/Makefile b/cargo/top/dv/LISTest/lis/BIST_LISFixed_POUT/Makefile
new file mode 100644
index 0000000..175e596
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/BIST_LISFixed_POUT/Makefile
@@ -0,0 +1,54 @@
+CARAVEL_PATH = ./../../../../../..
+
+FIRMWARE_PATH = ../..
+RTL_PATH = $(CARAVEL_PATH)/verilog/rtl
+IP_PATH = $(CARAVEL_PATH)/verilog/ip
+BEHAVIOURAL_MODELS = ../../ 
+
+CARGO_PATH   = $(CARAVEL_PATH)/cargo
+WB2AXI_PATH  = $(CARAVEL_PATH)/cargo/wb2axip/rtl
+PROJECT_PATH = $(CARAVEL_PATH)/cargo/lis/rtl/LISTest
+TOP_PATH     = $(CARAVEL_PATH)/cargo/top/rtl/LISTest
+
+GCC_PATH?=$(RISCV32)/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+LIS_SIZE?=24 # Pass fft size to testbench and c code
+
+.SUFFIXES:
+
+PATTERN = BIST_LISFixed_POUT
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -DSIM -DLIS_SIZE=$(LIS_SIZE) -I $(BEHAVIOURAL_MODELS) \
+	-I $(WB2AXI_PATH)  \
+	-I $(PROJECT_PATH) \
+	-I $(TOP_PATH) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -DLIS_SIZE=$(LIS_SIZE) -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.txt
+
+.PHONY: clean hex all
diff --git a/cargo/top/dv/LISTest/lis/BIST_LISInput_POUT/BIST_LISInput_POUT.c b/cargo/top/dv/LISTest/lis/BIST_LISInput_POUT/BIST_LISInput_POUT.c
new file mode 100644
index 0000000..8c98398
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/BIST_LISInput_POUT/BIST_LISInput_POUT.c
@@ -0,0 +1,63 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../../lisDefs.h"
+
+/*
+	LIS Test:
+*/
+
+
+void main()
+{
+	// Configure GPIO pins
+        reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+        reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+
+        reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_6  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+
+        bistAddress_reg(2*BEATBYTES) = 0x1; // configure counter to be active
+        bistAddress_reg(3*BEATBYTES) = 0x1; // configure counter to be up counter
+  
+        lisInputMuxAddress0_reg(0) = 0x0;
+        lisInputAddress_reg(4*BEATBYTES) = LIS_SIZE/2;
+        lisFIFOMuxAddress0_reg(BEATBYTES) = 0x0;
+        lisFixedMuxAddress0_reg(BEATBYTES) = 0x0;
+  
+        // configure fixed -> outMux
+        outMuxAddress_reg(0) = 0x1;
+        // configure bist_split -> out_mux
+        outMuxAddress_reg(2*BEATBYTES) = 0x3;
+  
+        // enable bist
+        bistAddress_reg(0) =  0x1;
+  
+}
+
diff --git a/cargo/top/dv/LISTest/lis/BIST_LISInput_POUT/BIST_LISInput_POUT_tb.v b/cargo/top/dv/LISTest/lis/BIST_LISInput_POUT/BIST_LISInput_POUT_tb.v
new file mode 100644
index 0000000..9362657
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/BIST_LISInput_POUT/BIST_LISInput_POUT_tb.v
@@ -0,0 +1,176 @@
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+
+module BIST_LISInput_POUT_tb;
+	// declare file for writing data
+	integer file;
+	
+	// Golden data
+	reg [7:0] goldenData [0:4*`LIS_SIZE-1];
+
+	// clk, rst, power signals
+	reg clock;
+    reg RSTB;
+	reg power1, power2;
+
+	// testbench signals
+    wire 		gpio;
+    wire [37:0] mprj_io;
+
+	// Output stream data wires
+	reg 	    out_ready = 0;
+	wire 	    out_valid;
+	wire  [7:0] out_data;
+	reg   [7:0] out_temp;
+
+	// Input stream data wires
+	wire 	    in_ready;
+	reg 	    in_valid = 0;
+	reg  [7:0]  in_data = 8'h04;
+	reg			in_last = 0;
+
+	reg [15:0] dataCounter = 16'b0;
+
+	// Assign wires
+	assign mprj_io[11]  = out_ready;
+	assign out_valid    = mprj_io[12];
+	assign out_data     = mprj_io[20:13];
+
+	assign in_ready 	= mprj_io[0];
+	assign mprj_io[1]   = in_valid;
+	assign mprj_io[9:2] = in_data[7:0];
+	assign mprj_io[10]  = in_last;
+
+	
+	// toggle clock
+	always #500 clock <= (clock === 1'b0);
+
+	// Read golden data
+	initial $readmemh("./../../../../../../cargo/lis/test_run_dir/LISTest/BIST_LISInput_POUT/output.txt", goldenData);
+
+	// open file for writting
+	initial begin
+		$printtimescale(BIST_LISInput_POUT_tb);
+		file = $fopen("output.txt","w");
+		if (file) $display("File was opened successfully : %0d", file);
+    	else $display("File was NOT opened successfully : %0d", file);
+	end
+
+	initial begin
+		clock = 0;
+		#500 out_ready = 1'b1; // Set out_ready
+	end
+
+
+	// Check outStream.ready and outStream.valid and collect data
+	always @ (posedge clock) begin
+		if (out_ready == 1'b1 && out_valid == 1'b1) begin
+			$fwriteh(file, "%h\n" ,out_data);
+			if (out_data != goldenData[dataCounter]) begin
+				$display("%c[1;31m",27);
+				$display ("Monitor: Test BIST_LISInput_POUT failed!!! Read data was %h, but should be %h.", out_data, goldenData[dataCounter]);
+				$display("%c[0m",27);
+				$fclose(file); 
+				$finish;
+			end
+			dataCounter <= dataCounter + 1'b1;
+		end
+	end
+
+	initial begin
+		$dumpfile("BIST_LISInput_POUT.vcd");
+		$dumpvars(0, BIST_LISInput_POUT_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Test BIST_LISInput_POUT Failed!!! Timeout.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	// Check if enough data was send, and if so terminate test
+	initial begin
+		wait(dataCounter == 16'd 4*`LIS_SIZE);
+		$display("%c[1;32m",27);
+		$display("Monitor: Test BIST_LISInput_POUT passed.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#10000;
+		RSTB <= 1'b1;	    // Release reset
+		#20000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("BIST_LISInput_POUT.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/cargo/top/dv/LISTest/lis/BIST_LISInput_POUT/Makefile b/cargo/top/dv/LISTest/lis/BIST_LISInput_POUT/Makefile
new file mode 100644
index 0000000..0f7775b
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/BIST_LISInput_POUT/Makefile
@@ -0,0 +1,54 @@
+CARAVEL_PATH = ./../../../../../..
+
+FIRMWARE_PATH = ../..
+RTL_PATH = $(CARAVEL_PATH)/verilog/rtl
+IP_PATH = $(CARAVEL_PATH)/verilog/ip
+BEHAVIOURAL_MODELS = ../../ 
+
+CARGO_PATH   = $(CARAVEL_PATH)/cargo
+WB2AXI_PATH  = $(CARAVEL_PATH)/cargo/wb2axip/rtl
+PROJECT_PATH = $(CARAVEL_PATH)/cargo/lis/rtl/LISTest
+TOP_PATH     = $(CARAVEL_PATH)/cargo/top/rtl/LISTest
+
+GCC_PATH?=$(RISCV32)/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+LIS_SIZE?=24 # Pass fft size to testbench and c code
+
+.SUFFIXES:
+
+PATTERN = BIST_LISInput_POUT
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -DSIM -DLIS_SIZE=$(LIS_SIZE) -I $(BEHAVIOURAL_MODELS) \
+	-I $(WB2AXI_PATH)  \
+	-I $(PROJECT_PATH) \
+	-I $(TOP_PATH) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -DLIS_SIZE=$(LIS_SIZE) -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.txt
+
+.PHONY: clean hex all
diff --git a/cargo/top/dv/LISTest/lis/Makefile b/cargo/top/dv/LISTest/lis/Makefile
new file mode 100644
index 0000000..61be999
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/Makefile
@@ -0,0 +1,19 @@
+# ---- Test patterns ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = BIST_LISInput_POUT BIST_LISFixed_POUT BIST_LISFIFO_POUT PIN_LISInput_POUT PIN_LISFixed_POUT PIN_LISFIFO_POUT
+
+all:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+	done
+
+clean:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		rm -f verify.log; \
+		( cd $$i && make clean ) ; \
+	done
+
+.PHONY: clean all
diff --git a/cargo/top/dv/LISTest/lis/PIN_LISFIFO_POUT/Makefile b/cargo/top/dv/LISTest/lis/PIN_LISFIFO_POUT/Makefile
new file mode 100644
index 0000000..c424429
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/PIN_LISFIFO_POUT/Makefile
@@ -0,0 +1,54 @@
+CARAVEL_PATH = ./../../../../../..
+
+FIRMWARE_PATH = ../..
+RTL_PATH = $(CARAVEL_PATH)/verilog/rtl
+IP_PATH = $(CARAVEL_PATH)/verilog/ip
+BEHAVIOURAL_MODELS = ../../ 
+
+CARGO_PATH   = $(CARAVEL_PATH)/cargo
+WB2AXI_PATH  = $(CARAVEL_PATH)/cargo/wb2axip/rtl
+PROJECT_PATH = $(CARAVEL_PATH)/cargo/lis/rtl/LISTest
+TOP_PATH     = $(CARAVEL_PATH)/cargo/top/rtl/LISTest
+
+GCC_PATH?=$(RISCV32)/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+LIS_SIZE?=24 # Pass fft size to testbench and c code
+
+.SUFFIXES:
+
+PATTERN = PIN_LISFIFO_POUT
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -DSIM -DLIS_SIZE=$(LIS_SIZE) -I $(BEHAVIOURAL_MODELS) \
+	-I $(WB2AXI_PATH)  \
+	-I $(PROJECT_PATH) \
+	-I $(TOP_PATH) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -DLIS_SIZE=$(LIS_SIZE) -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.txt
+
+.PHONY: clean hex all
diff --git a/cargo/top/dv/LISTest/lis/PIN_LISFIFO_POUT/PIN_LISFIFO_POUT.c b/cargo/top/dv/LISTest/lis/PIN_LISFIFO_POUT/PIN_LISFIFO_POUT.c
new file mode 100644
index 0000000..d6a1627
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/PIN_LISFIFO_POUT/PIN_LISFIFO_POUT.c
@@ -0,0 +1,55 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../../lisDefs.h"
+
+/*
+	LIS Test:
+*/
+
+
+void main()
+{
+	// Configure GPIO pins
+        reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+        reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+
+        reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_6  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+  
+        lisFIFOMuxAddress0_reg(0) = 0x1;
+        lisFIFOAddress_reg(4*BEATBYTES) = LIS_SIZE/2;
+        lisInputMuxAddress0_reg(BEATBYTES) = 0x1;
+        lisFixedMuxAddress0_reg(BEATBYTES) = 0x1;
+  
+        // configure fixed -> outMux
+        outMuxAddress_reg(0) = 0x0;
+        // configure bist_split -> out_mux
+        outMuxAddress_reg(2*BEATBYTES) = 0x4;
+}
diff --git a/cargo/top/dv/LISTest/lis/PIN_LISFIFO_POUT/PIN_LISFIFO_POUT_tb.v b/cargo/top/dv/LISTest/lis/PIN_LISFIFO_POUT/PIN_LISFIFO_POUT_tb.v
new file mode 100644
index 0000000..5f9f39f
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/PIN_LISFIFO_POUT/PIN_LISFIFO_POUT_tb.v
@@ -0,0 +1,190 @@
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+
+module PIN_LISFIFO_POUT_tb;
+	// declare file for writing data
+	integer file;
+	
+	// input data to send
+	reg [7:0] inputData [0:4*`LIS_SIZE-1];
+
+	// Golden data
+	reg [7:0] goldenData [0:4*`LIS_SIZE-1];
+
+	// clk, rst, power signals
+	reg clock;
+    reg RSTB;
+	reg power1, power2;
+
+	// testbench signals
+    wire 		gpio;
+    wire [37:0] mprj_io;
+
+	// Output stream data wires
+	reg 	    out_ready = 0;
+	wire 	    out_valid;
+	wire  [7:0] out_data;
+
+	// Input stream data wires
+	wire 	    in_ready;
+	reg 	    in_valid = 0;
+	reg  [7:0]  in_data = 8'h04;
+	reg			in_last = 0;
+
+	reg [15:0] dataCounter = 16'b0;
+	reg [15:0] dataSentCounter = 16'b0;
+
+	// Assign wires
+	assign mprj_io[11]  = out_ready;
+	assign out_valid    = mprj_io[12];
+	assign out_data     = mprj_io[20:13];
+
+	assign in_ready 	= mprj_io[0];
+	assign mprj_io[1]   = in_valid;
+	assign mprj_io[9:2] = in_data[7:0];
+	assign mprj_io[10]  = in_last;
+
+	
+	// toggle clock
+	always #500 clock <= (clock === 1'b0);
+
+	// Read input data
+	initial $readmemh("./../../../../../../cargo/lis/test_run_dir/LISTest/PIN_LISFIFO_POUT/input.txt", inputData);
+
+	// Read golden data
+	initial $readmemh("./../../../../../../cargo/lis/test_run_dir/LISTest/PIN_LISFIFO_POUT/output.txt", goldenData);
+
+	// open file for writting
+	initial begin
+		$printtimescale(PIN_LISFIFO_POUT_tb);
+		file = $fopen("output.txt","w");
+		if (file) $display("File was opened successfully : %0d", file);
+    	else $display("File was NOT opened successfully : %0d", file);
+	end
+
+	initial begin
+		clock = 0;
+		#500 out_ready = 1'b1; // Set out_ready
+	end
+
+	// Check inStream.ready and inStream.valid and send data
+	always @ (posedge clock) begin
+		if (in_ready == 1'b1) begin
+			in_valid = 1'b1;
+			in_data <= inputData[dataSentCounter % (4*`LIS_SIZE)];
+			dataSentCounter <= dataSentCounter + 1'b1;
+		end
+	end
+
+	// Check outStream.ready and outStream.valid and collect data
+	always @ (posedge clock) begin
+		if (out_ready == 1'b1 && out_valid == 1'b1) begin
+			$fwriteh(file, "%h\n" ,out_data);
+			if (out_data != goldenData[dataCounter]) begin
+				$display("%c[1;31m",27);
+				$display ("Monitor: Test PIN_LISFIFO_POUT failed!!! Read data was %h, but should be %h.", out_data, goldenData[dataCounter]);
+				$display("%c[0m",27);
+				$fclose(file); 
+				$finish;
+			end
+			dataCounter <= dataCounter + 1'b1;
+		end
+	end
+
+	initial begin
+		$dumpfile("PIN_LISFIFO_POUT.vcd");
+		$dumpvars(0, PIN_LISFIFO_POUT_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Test PIN_LISFIFO_POUT Failed!!! Timeout.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	// Check if enough data was send, and if so terminate test
+	initial begin
+		wait(dataCounter == 16'd 4*`LIS_SIZE);
+		$display("%c[1;32m",27);
+		$display("Monitor: Test PIN_LISFIFO_POUT passed.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#10000;
+		RSTB <= 1'b1;	    // Release reset
+		#20000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("PIN_LISFIFO_POUT.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/cargo/top/dv/LISTest/lis/PIN_LISFixed_POUT/Makefile b/cargo/top/dv/LISTest/lis/PIN_LISFixed_POUT/Makefile
new file mode 100644
index 0000000..89fe263
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/PIN_LISFixed_POUT/Makefile
@@ -0,0 +1,54 @@
+CARAVEL_PATH = ./../../../../../..
+
+FIRMWARE_PATH = ../..
+RTL_PATH = $(CARAVEL_PATH)/verilog/rtl
+IP_PATH = $(CARAVEL_PATH)/verilog/ip
+BEHAVIOURAL_MODELS = ../../ 
+
+CARGO_PATH   = $(CARAVEL_PATH)/cargo
+WB2AXI_PATH  = $(CARAVEL_PATH)/cargo/wb2axip/rtl
+PROJECT_PATH = $(CARAVEL_PATH)/cargo/lis/rtl/LISTest
+TOP_PATH     = $(CARAVEL_PATH)/cargo/top/rtl/LISTest
+
+GCC_PATH?=$(RISCV32)/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+LIS_SIZE?=24 # Pass fft size to testbench and c code
+
+.SUFFIXES:
+
+PATTERN = PIN_LISFixed_POUT
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -DSIM -DLIS_SIZE=$(LIS_SIZE) -I $(BEHAVIOURAL_MODELS) \
+	-I $(WB2AXI_PATH)  \
+	-I $(PROJECT_PATH) \
+	-I $(TOP_PATH) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -DLIS_SIZE=$(LIS_SIZE) -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.txt
+
+.PHONY: clean hex all
diff --git a/cargo/top/dv/LISTest/lis/PIN_LISFixed_POUT/PIN_LISFixed_POUT.c b/cargo/top/dv/LISTest/lis/PIN_LISFixed_POUT/PIN_LISFixed_POUT.c
new file mode 100644
index 0000000..5aac4b6
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/PIN_LISFixed_POUT/PIN_LISFixed_POUT.c
@@ -0,0 +1,56 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../../lisDefs.h"
+
+/*
+	LIS Test:
+*/
+
+
+void main()
+{
+	// Configure GPIO pins
+        reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+        reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+
+        reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_6  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+  
+        lisFixedMuxAddress0_reg(0) = 0x1;
+        lisFixedAddress_reg(4*BEATBYTES) = LIS_SIZE/2;
+        lisFIFOMuxAddress0_reg(BEATBYTES) = 0x1;
+        lisInputMuxAddress0_reg(BEATBYTES) = 0x1;
+  
+        // configure fixed -> outMux
+        outMuxAddress_reg(0) = 0x2;
+        // configure bist_split -> out_mux
+        outMuxAddress_reg(2*BEATBYTES) = 0x4;
+  
+}
\ No newline at end of file
diff --git a/cargo/top/dv/LISTest/lis/PIN_LISFixed_POUT/PIN_LISFixed_POUT_tb.v b/cargo/top/dv/LISTest/lis/PIN_LISFixed_POUT/PIN_LISFixed_POUT_tb.v
new file mode 100644
index 0000000..9c76dde
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/PIN_LISFixed_POUT/PIN_LISFixed_POUT_tb.v
@@ -0,0 +1,190 @@
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+
+module PIN_LISFixed_POUT_tb;
+	// declare file for writing data
+	integer file;
+	
+	// input data to send
+	reg [7:0] inputData [0:4*`LIS_SIZE-1];
+
+	// Golden data
+	reg [7:0] goldenData [0:4*`LIS_SIZE-1];
+
+	// clk, rst, power signals
+	reg clock;
+    reg RSTB;
+	reg power1, power2;
+
+	// testbench signals
+    wire 		gpio;
+    wire [37:0] mprj_io;
+
+	// Output stream data wires
+	reg 	    out_ready = 0;
+	wire 	    out_valid;
+	wire  [7:0] out_data;
+
+	// Input stream data wires
+	wire 	    in_ready;
+	reg 	    in_valid = 0;
+	reg  [7:0]  in_data = 8'h04;
+	reg			in_last = 0;
+
+	reg [15:0] dataCounter = 16'b0;
+	reg [15:0] dataSentCounter = 16'b0;
+
+	// Assign wires
+	assign mprj_io[11]  = out_ready;
+	assign out_valid    = mprj_io[12];
+	assign out_data     = mprj_io[20:13];
+
+	assign in_ready 	= mprj_io[0];
+	assign mprj_io[1]   = in_valid;
+	assign mprj_io[9:2] = in_data[7:0];
+	assign mprj_io[10]  = in_last;
+
+	
+	// toggle clock
+	always #500 clock <= (clock === 1'b0);
+
+	// Read input data
+	initial $readmemh("./../../../../../../cargo/lis/test_run_dir/LISTest/PIN_LISFixed_POUT/input.txt", inputData);
+
+	// Read golden data
+	initial $readmemh("./../../../../../../cargo/lis/test_run_dir/LISTest/PIN_LISFixed_POUT/output.txt", goldenData);
+
+	// open file for writting
+	initial begin
+		$printtimescale(PIN_LISFixed_POUT_tb);
+		file = $fopen("output.txt","w");
+		if (file) $display("File was opened successfully : %0d", file);
+    	else $display("File was NOT opened successfully : %0d", file);
+	end
+
+	initial begin
+		clock = 0;
+		#500 out_ready = 1'b1; // Set out_ready
+	end
+
+	// Check inStream.ready and inStream.valid and send data
+	always @ (posedge clock) begin
+		if (in_ready == 1'b1) begin
+			in_valid = 1'b1;
+			in_data <= inputData[dataSentCounter % (4*`LIS_SIZE)];
+			dataSentCounter <= dataSentCounter + 1'b1;
+		end
+	end
+
+	// Check outStream.ready and outStream.valid and collect data
+	always @ (posedge clock) begin
+		if (out_ready == 1'b1 && out_valid == 1'b1) begin
+			$fwriteh(file, "%h\n" ,out_data);
+			if (out_data != goldenData[dataCounter]) begin
+				$display("%c[1;31m",27);
+				$display ("Monitor: Test PIN_LISFixed_POUT failed!!! Read data was %h, but should be %h.", out_data, goldenData[dataCounter]);
+				$display("%c[0m",27);
+				$fclose(file); 
+				$finish;
+			end
+			dataCounter <= dataCounter + 1'b1;
+		end
+	end
+
+	initial begin
+		$dumpfile("PIN_LISFixed_POUT.vcd");
+		$dumpvars(0, PIN_LISFixed_POUT_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Test PIN_LISFixed_POUT Failed!!! Timeout.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	// Check if enough data was send, and if so terminate test
+	initial begin
+		wait(dataCounter == 16'd 4*`LIS_SIZE);
+		$display("%c[1;32m",27);
+		$display("Monitor: Test PIN_LISFixed_POUT passed.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#10000;
+		RSTB <= 1'b1;	    // Release reset
+		#20000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("PIN_LISFixed_POUT.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/cargo/top/dv/LISTest/lis/PIN_LISInput_POUT/Makefile b/cargo/top/dv/LISTest/lis/PIN_LISInput_POUT/Makefile
new file mode 100644
index 0000000..0c962e5
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/PIN_LISInput_POUT/Makefile
@@ -0,0 +1,54 @@
+CARAVEL_PATH = ./../../../../../..
+
+FIRMWARE_PATH = ../..
+RTL_PATH = $(CARAVEL_PATH)/verilog/rtl
+IP_PATH = $(CARAVEL_PATH)/verilog/ip
+BEHAVIOURAL_MODELS = ../../ 
+
+CARGO_PATH   = $(CARAVEL_PATH)/cargo
+WB2AXI_PATH  = $(CARAVEL_PATH)/cargo/wb2axip/rtl
+PROJECT_PATH = $(CARAVEL_PATH)/cargo/lis/rtl/LISTest
+TOP_PATH     = $(CARAVEL_PATH)/cargo/top/rtl/LISTest
+
+GCC_PATH?=$(RISCV32)/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+LIS_SIZE?=24 # Pass fft size to testbench and c code
+
+.SUFFIXES:
+
+PATTERN = PIN_LISInput_POUT
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -DSIM -DLIS_SIZE=$(LIS_SIZE) -I $(BEHAVIOURAL_MODELS) \
+	-I $(WB2AXI_PATH)  \
+	-I $(PROJECT_PATH) \
+	-I $(TOP_PATH) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -DLIS_SIZE=$(LIS_SIZE) -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.txt
+
+.PHONY: clean hex all
diff --git a/cargo/top/dv/LISTest/lis/PIN_LISInput_POUT/PIN_LISInput_POUT.c b/cargo/top/dv/LISTest/lis/PIN_LISInput_POUT/PIN_LISInput_POUT.c
new file mode 100644
index 0000000..390f2b6
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/PIN_LISInput_POUT/PIN_LISInput_POUT.c
@@ -0,0 +1,55 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../../lisDefs.h"
+
+/*
+	LIS Test:
+*/
+
+
+void main()
+{
+	// Configure GPIO pins
+        reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+        reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+
+        reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_6  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+  
+        lisInputMuxAddress0_reg(0) = 0x1;
+        lisInputAddress_reg(4*BEATBYTES) = LIS_SIZE/2;
+        lisFIFOMuxAddress0_reg(BEATBYTES) = 0x1;
+        lisFixedMuxAddress0_reg(BEATBYTES) = 0x1;
+  
+        // configure fixed -> outMux
+        outMuxAddress_reg(0) = 0x1;
+        // configure bist_split -> out_mux
+        outMuxAddress_reg(2*BEATBYTES) = 0x4;
+}
\ No newline at end of file
diff --git a/cargo/top/dv/LISTest/lis/PIN_LISInput_POUT/PIN_LISInput_POUT_tb.v b/cargo/top/dv/LISTest/lis/PIN_LISInput_POUT/PIN_LISInput_POUT_tb.v
new file mode 100644
index 0000000..e2f5275
--- /dev/null
+++ b/cargo/top/dv/LISTest/lis/PIN_LISInput_POUT/PIN_LISInput_POUT_tb.v
@@ -0,0 +1,190 @@
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+
+module PIN_LISInput_POUT_tb;
+	// declare file for writing data
+	integer file;
+	
+	// input data to send
+	reg [7:0] inputData [0:4*`LIS_SIZE-1];
+
+	// Golden data
+	reg [7:0] goldenData [0:4*`LIS_SIZE-1];
+
+	// clk, rst, power signals
+	reg clock;
+    reg RSTB;
+	reg power1, power2;
+
+	// testbench signals
+    wire 		gpio;
+    wire [37:0] mprj_io;
+
+	// Output stream data wires
+	reg 	    out_ready = 0;
+	wire 	    out_valid;
+	wire  [7:0] out_data;
+
+	// Input stream data wires
+	wire 	    in_ready;
+	reg 	    in_valid = 0;
+	reg  [7:0]  in_data = 8'h04;
+	reg			in_last = 0;
+
+	reg [15:0] dataCounter = 16'b0;
+	reg [15:0] dataSentCounter = 16'b0;
+
+	// Assign wires
+	assign mprj_io[11]  = out_ready;
+	assign out_valid    = mprj_io[12];
+	assign out_data     = mprj_io[20:13];
+
+	assign in_ready 	= mprj_io[0];
+	assign mprj_io[1]   = in_valid;
+	assign mprj_io[9:2] = in_data[7:0];
+	assign mprj_io[10]  = in_last;
+
+	
+	// toggle clock
+	always #500 clock <= (clock === 1'b0);
+
+	// Read input data
+	initial $readmemh("./../../../../../../cargo/lis/test_run_dir/LISTest/PIN_LISInput_POUT/input.txt", inputData);
+
+	// Read golden data
+	initial $readmemh("./../../../../../../cargo/lis/test_run_dir/LISTest/PIN_LISInput_POUT/output.txt", goldenData);
+
+	// open file for writting
+	initial begin
+		$printtimescale(PIN_LISInput_POUT_tb);
+		file = $fopen("output.txt","w");
+		if (file) $display("File was opened successfully : %0d", file);
+    	else $display("File was NOT opened successfully : %0d", file);
+	end
+
+	initial begin
+		clock = 0;
+		#500 out_ready = 1'b1; // Set out_ready
+	end
+
+	// Check inStream.ready and inStream.valid and send data
+	always @ (posedge clock) begin
+		if (in_ready == 1'b1) begin
+			in_valid = 1'b1;
+			in_data <= inputData[dataSentCounter % (4*`LIS_SIZE)];
+			dataSentCounter <= dataSentCounter + 1'b1;
+		end
+	end
+
+	// Check outStream.ready and outStream.valid and collect data
+	always @ (posedge clock) begin
+		if (out_ready == 1'b1 && out_valid == 1'b1) begin
+			$fwriteh(file, "%h\n" ,out_data);
+			if (out_data != goldenData[dataCounter]) begin
+				$display("%c[1;31m",27);
+				$display ("Monitor: Test PIN_LISInput_POUT failed!!! Read data was %h, but should be %h.", out_data, goldenData[dataCounter]);
+				$display("%c[0m",27);
+				$fclose(file); 
+				$finish;
+			end
+			dataCounter <= dataCounter + 1'b1;
+		end
+	end
+
+	initial begin
+		$dumpfile("PIN_LISInput_POUT.vcd");
+		$dumpvars(0, PIN_LISInput_POUT_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Test PIN_LISInput_POUT Failed!!! Timeout.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	// Check if enough data was send, and if so terminate test
+	initial begin
+		wait(dataCounter == 16'd 4*`LIS_SIZE);
+		$display("%c[1;32m",27);
+		$display("Monitor: Test PIN_LISInput_POUT passed.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#10000;
+		RSTB <= 1'b1;	    // Release reset
+		#20000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("PIN_LISInput_POUT.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/cargo/top/dv/LISTest/lisDefs.h b/cargo/top/dv/LISTest/lisDefs.h
new file mode 100644
index 0000000..1110616
--- /dev/null
+++ b/cargo/top/dv/LISTest/lisDefs.h
@@ -0,0 +1,66 @@
+#ifndef _LISDEF_H_
+#define _LISDEF_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// Helper functions
+#define _AC(X,Y)        (X##Y)
+
+#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
+
+#define BEATBYTES 4
+
+#define inSplitAddress       _AC(0x30000000,UL)
+#define lisFIFOAddress       _AC(0x30001000,UL)
+#define lisFIFOMuxAddress0   _AC(0x30001100,UL)
+#define lisFixedAddress      _AC(0x30002000,UL)
+#define lisFixedMuxAddress0  _AC(0x30002100,UL)
+#define lisInputAddress      _AC(0x30003000,UL)
+#define lisInputMuxAddress0  _AC(0x30003100,UL)
+#define bistAddress          _AC(0x30004000,UL)
+#define bistSplitAddress     _AC(0x30004100,UL)
+#define outMuxAddress        _AC(0x30005000,UL)
+#define outSplitAddress      _AC(0x30005010,UL)
+#define uartParams           _AC(0x30006000,UL)
+#define uRxSplitAddress      _AC(0x30006100,UL)
+
+
+#define inSplitAddress_reg(offset)         _REG32(inSplitAddress, offset)
+#define lisFIFOAddress_reg(offset)         _REG32(lisFIFOAddress, offset)
+#define lisFIFOMuxAddress0_reg(offset)     _REG32(lisFIFOMuxAddress0, offset)
+#define lisFixedAddress_reg(offset)        _REG32(lisFixedAddress, offset)
+#define lisFixedMuxAddress0_reg(offset)    _REG32(lisFixedMuxAddress0, offset)
+#define lisInputAddress_reg(offset)        _REG32(lisInputAddress, offset)
+#define lisInputMuxAddress0_reg(offset)    _REG32(lisInputMuxAddress0, offset)
+#define bistAddress_reg(offset)            _REG32(bistAddress, offset)
+#define bistSplitAddress_reg(offset)       _REG32(bistSplitAddress, offset)
+#define outMuxAddress_reg(offset)          _REG32(outMuxAddress, offset)
+#define outSplitAddress_reg(offset)        _REG32(outSplitAddress, offset)
+#define uartParams_reg(offset)             _REG32(uartParams, offset)
+#define uRxSplitAddress_reg(offset)        _REG32(uRxSplitAddress, offset)
+
+/* Register offsets */
+#define uart_txfifo     0x00
+#define uart_rxfifo 	0x04
+#define uart_txctrl 	0x08
+#define uart_txmark 	0x0a
+#define uart_rxctrl 	0x0c
+#define uart_rxmark		0x0e
+
+#define uart_ie     	0x10
+#define uart_ip    		0x14
+#define uart_div    	0x18
+#define uart_parity		0x1c
+#define uart_wire4		0x20
+#define uart_either8or9 0x24
+
+#define mux_output_0    0x0*BEATBYTES
+#define mux_output_1    0x1*BEATBYTES
+#define mux_output_2    0x2*BEATBYTES
+
+#define spl_ctrl        0x0*BEATBYTES
+#define spl_mask        0x1*BEATBYTES
+
+// --------------------------------------------------------
+#endif
diff --git a/cargo/top/dv/LISTest/plot.py b/cargo/top/dv/LISTest/plot.py
new file mode 100644
index 0000000..1b65e1b
--- /dev/null
+++ b/cargo/top/dv/LISTest/plot.py
@@ -0,0 +1,14 @@
+import sys
+import matplotlib.pyplot as plt
+
+file1 = open(sys.argv[1],"r")  
+data = file1.read()
+file1.close()
+
+dataInt = []
+for i in range(len(data)//5):
+    dataInt.append(int(data[i*5:i*5+4],16))
+
+plt.plot(dataInt)
+plt.ylabel('N')
+plt.show()
\ No newline at end of file
diff --git a/cargo/top/dv/LISTest/sections.lds b/cargo/top/dv/LISTest/sections.lds
new file mode 100644
index 0000000..8da9aae
--- /dev/null
+++ b/cargo/top/dv/LISTest/sections.lds
@@ -0,0 +1,58 @@
+MEMORY {
+	FLASH (rx)	: ORIGIN = 0x10000000, LENGTH = 0x400000 	/* 4MB */
+	RAM(xrw)	: ORIGIN = 0x00000000, LENGTH = 0x0400		/* 256 words (1 KB) */ 
+}
+
+SECTIONS {
+	/* The program code and other data goes into FLASH */
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)	/* .text sections (code) */
+		*(.text*)	/* .text* sections (code) */
+		*(.rodata)	/* .rodata sections (constants, strings, etc.) */
+		*(.rodata*)	/* .rodata* sections (constants, strings, etc.) */
+		*(.srodata)	/* .srodata sections (constants, strings, etc.) */
+		*(.srodata*)	/* .srodata*sections (constants, strings, etc.) */
+		. = ALIGN(4);
+		_etext = .;		/* define a global symbol at end of code */
+		_sidata = _etext;	/* This is used by the startup to initialize data */
+	} >FLASH
+
+	/* Initialized data section */
+	.data : AT ( _sidata )
+	{
+		. = ALIGN(4);
+		_sdata = .;
+		_ram_start = .;
+		. = ALIGN(4);
+		*(.data)
+		*(.data*)
+		*(.sdata)
+		*(.sdata*)
+		. = ALIGN(4);
+		_edata = .;
+	} >RAM
+
+	/* Uninitialized data section */
+	.bss :
+	{
+		. = ALIGN(4);
+		_sbss = .;
+		*(.bss)
+		*(.bss*)
+		*(.sbss)
+		*(.sbss*)
+		*(COMMON)
+
+		. = ALIGN(4);
+		_ebss = .;
+	} >RAM
+
+	/* Define the start of the heap */
+	.heap :
+	{
+		. = ALIGN(4);
+		_heap_start = .;
+	} >RAM
+}
diff --git a/cargo/top/dv/LISTest/spiflash.v b/cargo/top/dv/LISTest/spiflash.v
new file mode 100644
index 0000000..d4a82d9
--- /dev/null
+++ b/cargo/top/dv/LISTest/spiflash.v
@@ -0,0 +1,414 @@
+`default_nettype none
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+//
+// Simple SPI flash simulation model
+//
+// This model samples io input signals 1ns before the SPI clock edge and
+// updates output signals 1ns after the SPI clock edge.
+//
+// Supported commands:
+//    AB, B9, FF, 03, BB, EB, ED
+//
+// Well written SPI flash data sheets:
+//    Cypress S25FL064L http://www.cypress.com/file/316661/download
+//    Cypress S25FL128L http://www.cypress.com/file/316171/download
+//
+
+module spiflash #(
+	parameter FILENAME = "firmware.hex"
+)(
+	input csb,
+	input clk,
+	inout io0, // MOSI
+	inout io1, // MISO
+	inout io2,
+	inout io3
+);
+	localparam verbose = 0;
+	localparam integer latency = 8;
+	
+	reg [7:0] buffer;
+	integer bitcount = 0;
+	integer bytecount = 0;
+	integer dummycount = 0;
+
+	reg [7:0] spi_cmd;
+	reg [7:0] xip_cmd = 0;
+	reg [23:0] spi_addr;
+
+	reg [7:0] spi_in;
+	reg [7:0] spi_out;
+	reg spi_io_vld;
+
+	reg powered_up = 0;
+
+	localparam [3:0] mode_spi         = 1;
+	localparam [3:0] mode_dspi_rd     = 2;
+	localparam [3:0] mode_dspi_wr     = 3;
+	localparam [3:0] mode_qspi_rd     = 4;
+	localparam [3:0] mode_qspi_wr     = 5;
+	localparam [3:0] mode_qspi_ddr_rd = 6;
+	localparam [3:0] mode_qspi_ddr_wr = 7;
+
+	reg [3:0] mode = 0;
+	reg [3:0] next_mode = 0;
+
+	reg io0_oe = 0;
+	reg io1_oe = 0;
+	reg io2_oe = 0;
+	reg io3_oe = 0;
+
+	reg io0_dout = 0;
+	reg io1_dout = 0;
+	reg io2_dout = 0;
+	reg io3_dout = 0;
+
+	assign #1 io0 = io0_oe ? io0_dout : 1'bz;
+	assign #1 io1 = io1_oe ? io1_dout : 1'bz;
+	assign #1 io2 = io2_oe ? io2_dout : 1'bz;
+	assign #1 io3 = io3_oe ? io3_dout : 1'bz;
+
+	wire io0_delayed;
+	wire io1_delayed;
+	wire io2_delayed;
+	wire io3_delayed;
+
+	assign #1 io0_delayed = io0;
+	assign #1 io1_delayed = io1;
+	assign #1 io2_delayed = io2;
+	assign #1 io3_delayed = io3;
+
+	// 16 MB (128Mb) Flash
+	reg [7:0] memory [0:16*1024*1024-1];
+
+	initial begin
+		$display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+			memory[1048576], memory[1048577], memory[1048578],
+			memory[1048579], memory[1048580]);
+		$display("Reading %s",  FILENAME);
+		$readmemh(FILENAME, memory);
+		$display("%s loaded into memory", FILENAME);
+		$display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+			memory[1048576], memory[1048577], memory[1048578],
+			memory[1048579], memory[1048580]);
+	end
+
+	task spi_action;
+		begin
+			spi_in = buffer;
+
+			if (bytecount == 1) begin
+				spi_cmd = buffer;
+
+				if (spi_cmd == 8'h ab)
+					powered_up = 1;
+
+				if (spi_cmd == 8'h b9)
+					powered_up = 0;
+
+				if (spi_cmd == 8'h ff)
+					xip_cmd = 0;
+			end
+
+			if (powered_up && spi_cmd == 'h 03) begin
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount >= 4) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			if (powered_up && spi_cmd == 'h bb) begin
+				if (bytecount == 1)
+					mode = mode_dspi_rd;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount == 5) begin
+					xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+					mode = mode_dspi_wr;
+					dummycount = latency;
+				end
+
+				if (bytecount >= 5) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			if (powered_up && spi_cmd == 'h eb) begin
+				if (bytecount == 1)
+					mode = mode_qspi_rd;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount == 5) begin
+					xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+					mode = mode_qspi_wr;
+					dummycount = latency;
+				end
+
+				if (bytecount >= 5) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			if (powered_up && spi_cmd == 'h ed) begin
+				if (bytecount == 1)
+					next_mode = mode_qspi_ddr_rd;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount == 5) begin
+					xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+					mode = mode_qspi_ddr_wr;
+					dummycount = latency;
+				end
+
+				if (bytecount >= 5) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			spi_out = buffer;
+			spi_io_vld = 1;
+
+			if (verbose) begin
+				if (bytecount == 1)
+					$write("<SPI-START>");
+				$write("<SPI:%02x:%02x>", spi_in, spi_out);
+			end
+
+		end
+	endtask
+
+	task ddr_rd_edge;
+		begin
+			buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed};
+			bitcount = bitcount + 4;
+			if (bitcount == 8) begin
+				bitcount = 0;
+				bytecount = bytecount + 1;
+				spi_action;
+			end
+		end
+	endtask
+
+	task ddr_wr_edge;
+		begin
+			io0_oe = 1;
+			io1_oe = 1;
+			io2_oe = 1;
+			io3_oe = 1;
+
+			io0_dout = buffer[4];
+			io1_dout = buffer[5];
+			io2_dout = buffer[6];
+			io3_dout = buffer[7];
+
+			buffer = {buffer, 4'h 0};
+			bitcount = bitcount + 4;
+			if (bitcount == 8) begin
+				bitcount = 0;
+				bytecount = bytecount + 1;
+				spi_action;
+			end
+		end
+	endtask
+
+	always @(csb) begin
+		if (csb) begin
+			if (verbose) begin
+				$display("");
+				$fflush;
+			end
+			buffer = 0;
+			bitcount = 0;
+			bytecount = 0;
+			mode = mode_spi;
+			io0_oe = 0;
+			io1_oe = 0;
+			io2_oe = 0;
+			io3_oe = 0;
+		end else
+		if (xip_cmd) begin
+			buffer = xip_cmd;
+			bitcount = 0;
+			bytecount = 1;
+			spi_action;
+		end
+	end
+
+	always @(csb, clk) begin
+		spi_io_vld = 0;
+		if (!csb && !clk) begin
+			if (dummycount > 0) begin
+				io0_oe = 0;
+				io1_oe = 0;
+				io2_oe = 0;
+				io3_oe = 0;
+			end else
+			case (mode)
+				mode_spi: begin
+					io0_oe = 0;
+					io1_oe = 1;
+					io2_oe = 0;
+					io3_oe = 0;
+					io1_dout = buffer[7];
+				end
+				mode_dspi_rd: begin
+					io0_oe = 0;
+					io1_oe = 0;
+					io2_oe = 0;
+					io3_oe = 0;
+				end
+				mode_dspi_wr: begin
+					io0_oe = 1;
+					io1_oe = 1;
+					io2_oe = 0;
+					io3_oe = 0;
+					io0_dout = buffer[6];
+					io1_dout = buffer[7];
+				end
+				mode_qspi_rd: begin
+					io0_oe = 0;
+					io1_oe = 0;
+					io2_oe = 0;
+					io3_oe = 0;
+				end
+				mode_qspi_wr: begin
+					io0_oe = 1;
+					io1_oe = 1;
+					io2_oe = 1;
+					io3_oe = 1;
+					io0_dout = buffer[4];
+					io1_dout = buffer[5];
+					io2_dout = buffer[6];
+					io3_dout = buffer[7];
+				end
+				mode_qspi_ddr_rd: begin
+					ddr_rd_edge;
+				end
+				mode_qspi_ddr_wr: begin
+					ddr_wr_edge;
+				end
+			endcase
+			if (next_mode) begin
+				case (next_mode)
+					mode_qspi_ddr_rd: begin
+						io0_oe = 0;
+						io1_oe = 0;
+						io2_oe = 0;
+						io3_oe = 0;
+					end
+					mode_qspi_ddr_wr: begin
+						io0_oe = 1;
+						io1_oe = 1;
+						io2_oe = 1;
+						io3_oe = 1;
+						io0_dout = buffer[4];
+						io1_dout = buffer[5];
+						io2_dout = buffer[6];
+						io3_dout = buffer[7];
+					end
+				endcase
+				mode = next_mode;
+				next_mode = 0;
+			end
+		end
+	end
+
+	always @(posedge clk) begin
+		if (!csb) begin
+			if (dummycount > 0) begin
+				dummycount = dummycount - 1;
+			end else
+			case (mode)
+				mode_spi: begin
+					buffer = {buffer, io0};
+					bitcount = bitcount + 1;
+					if (bitcount == 8) begin
+						bitcount = 0;
+						bytecount = bytecount + 1;
+						spi_action;
+					end
+				end
+				mode_dspi_rd, mode_dspi_wr: begin
+					buffer = {buffer, io1, io0};
+					bitcount = bitcount + 2;
+					if (bitcount == 8) begin
+						bitcount = 0;
+						bytecount = bytecount + 1;
+						spi_action;
+					end
+				end
+				mode_qspi_rd, mode_qspi_wr: begin
+					buffer = {buffer, io3, io2, io1, io0};
+					bitcount = bitcount + 4;
+					if (bitcount == 8) begin
+						bitcount = 0;
+						bytecount = bytecount + 1;
+						spi_action;
+					end
+				end
+				mode_qspi_ddr_rd: begin
+					ddr_rd_edge;
+				end
+				mode_qspi_ddr_wr: begin
+					ddr_wr_edge;
+				end
+			endcase
+		end
+	end
+endmodule
diff --git a/cargo/top/dv/LISTest/start.s b/cargo/top/dv/LISTest/start.s
new file mode 100644
index 0000000..62a6f42
--- /dev/null
+++ b/cargo/top/dv/LISTest/start.s
@@ -0,0 +1,159 @@
+.section .text
+
+start:
+
+# zero-initialize register file
+addi x1, zero, 0
+# x2 (sp) is initialized by reset
+addi x3, zero, 0
+addi x4, zero, 0
+addi x5, zero, 0
+addi x6, zero, 0
+addi x7, zero, 0
+addi x8, zero, 0
+addi x9, zero, 0
+addi x10, zero, 0
+addi x11, zero, 0
+addi x12, zero, 0
+addi x13, zero, 0
+addi x14, zero, 0
+addi x15, zero, 0
+addi x16, zero, 0
+addi x17, zero, 0
+addi x18, zero, 0
+addi x19, zero, 0
+addi x20, zero, 0
+addi x21, zero, 0
+addi x22, zero, 0
+addi x23, zero, 0
+addi x24, zero, 0
+addi x25, zero, 0
+addi x26, zero, 0
+addi x27, zero, 0
+addi x28, zero, 0
+addi x29, zero, 0
+addi x30, zero, 0
+addi x31, zero, 0
+
+# zero initialize scratchpad memory
+# setmemloop:
+# sw zero, 0(x1)
+# addi x1, x1, 4
+# blt x1, sp, setmemloop
+
+# copy data section
+la a0, _sidata
+la a1, _sdata
+la a2, _edata
+bge a1, a2, end_init_data
+loop_init_data:
+lw a3, 0(a0)
+sw a3, 0(a1)
+addi a0, a0, 4
+addi a1, a1, 4
+blt a1, a2, loop_init_data
+end_init_data:
+
+# zero-init bss section
+la a0, _sbss
+la a1, _ebss
+bge a0, a1, end_init_bss
+loop_init_bss:
+sw zero, 0(a0)
+addi a0, a0, 4
+blt a0, a1, loop_init_bss
+end_init_bss:
+
+# call main
+call main
+loop:
+j loop
+
+.global flashio_worker_begin
+.global flashio_worker_end
+
+.balign 4
+
+flashio_worker_begin:
+# a0 ... data pointer
+# a1 ... data length
+# a2 ... optional WREN cmd (0 = disable)
+
+# address of SPI ctrl reg
+li   t0, 0x28000000
+
+# Set CS high, IO0 is output
+li   t1, 0x120
+sh   t1, 0(t0)
+
+# Enable Manual SPI Ctrl
+sb   zero, 3(t0)
+
+# Send optional WREN cmd
+beqz a2, flashio_worker_L1
+li   t5, 8
+andi t2, a2, 0xff
+flashio_worker_L4:
+srli t4, t2, 7
+sb   t4, 0(t0)
+ori  t4, t4, 0x10
+sb   t4, 0(t0)
+slli t2, t2, 1
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L4
+sb   t1, 0(t0)
+
+# SPI transfer
+flashio_worker_L1:
+
+# If byte count is zero, we're done
+beqz a1, flashio_worker_L3
+
+# Set t5 to count down 32 bits
+li   t5, 32
+# Load t2 from address a0 (4 bytes)
+lw   t2, 0(a0)
+
+flashio_worker_LY:
+# Set t6 to count down 8 bits
+li   t6, 8
+
+flashio_worker_L2:
+# Clock out the bit (msb first) on IO0 and read bit in from IO1
+srli t4, t2, 31
+sb   t4, 0(t0)
+ori  t4, t4, 0x10
+sb   t4, 0(t0)
+lbu  t4, 0(t0)
+andi t4, t4, 2
+srli t4, t4, 1
+slli t2, t2, 1
+or   t2, t2, t4
+
+# Decrement 32 bit count
+addi t5, t5, -1
+bnez t5, flashio_worker_LX
+
+sw   t2, 0(a0)
+addi a0, a0, 4
+lw   t2, 0(a0)
+
+flashio_worker_LX:
+addi t6, t6, -1
+bnez t6, flashio_worker_L2
+addi a1, a1, -1
+bnez a1, flashio_worker_LY
+
+beqz t5, flashio_worker_L3
+sw   t2, 0(a0)
+
+flashio_worker_L3:
+# Back to MEMIO mode
+li   t1, 0x80
+sb   t1, 3(t0)
+
+ret
+.balign 4
+flashio_worker_end:
+
diff --git a/cargo/top/dv/LISTest/stub.c b/cargo/top/dv/LISTest/stub.c
new file mode 100644
index 0000000..4d9c970
--- /dev/null
+++ b/cargo/top/dv/LISTest/stub.c
@@ -0,0 +1,12 @@
+void putchar(char c)
+{
+	if (c == '\n')
+		putchar('\r');
+	reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+	while (*p)
+		putchar(*(p++));
+}
\ No newline at end of file
diff --git a/cargo/top/dv/LISTest/tbuart.v b/cargo/top/dv/LISTest/tbuart.v
new file mode 100644
index 0000000..f623a60
--- /dev/null
+++ b/cargo/top/dv/LISTest/tbuart.v
@@ -0,0 +1,90 @@
+`default_nettype none
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+/* tbuart --- mimic an external UART display, operating at 9600 baud	*/
+/* and accepting ASCII characters for display.				*/
+
+/* To do:  Match a known UART 3.3V 16x2 LCD display.  However, it	*/
+/* should be possible on a testing system to interface to the UART	*/
+/* pins on a Raspberry Pi, also running at 3.3V.			*/
+
+module tbuart (
+	input  ser_rx
+);
+	reg [3:0] recv_state;
+	reg [2:0] recv_divcnt;
+	reg [7:0] recv_pattern;
+	reg [8*50-1:0] recv_buf_data;	// 50 characters.  Increase as needed for tests.
+
+	reg clk;
+
+	initial begin
+		clk <= 1'b0;
+		recv_state <= 0;
+		recv_divcnt <= 0;
+		recv_pattern <= 0;
+		recv_buf_data <= 0;
+	end
+
+	// NOTE:  Running at 3.0us clock period @ 5 clocks per bit = 15.0us per
+	// bit ~= 64 kbaud. Not tuned to any particular UART.  Most run at
+	// 9600 baud default and will bounce up to higher baud rates when
+	// passed specific command words.
+
+	always #1500 clk <= (clk === 1'b0);
+
+	always @(posedge clk) begin
+		recv_divcnt <= recv_divcnt + 1;
+		case (recv_state)
+			0: begin
+				if (!ser_rx)
+					recv_state <= 1;
+				recv_divcnt <= 0;
+			end
+			1: begin
+				if (2*recv_divcnt > 3'd3) begin
+					recv_state <= 2;
+					recv_divcnt <= 0;
+				end
+			end
+			10: begin
+				if (recv_divcnt > 3'd3) begin
+					// 0x0a = '\n'
+					if (recv_pattern == 8'h0a) begin
+						$display("output: %s", recv_buf_data);
+					end else begin
+						recv_buf_data <= {recv_buf_data, recv_pattern};
+					end
+					recv_state <= 0;
+				end
+			end
+			default: begin
+				if (recv_divcnt > 3'd3) begin
+					recv_pattern <= {ser_rx, recv_pattern[7:1]};
+					recv_state <= recv_state + 1;
+					recv_divcnt <= 0;
+				end
+			end
+		endcase
+	end
+
+endmodule
diff --git a/cargo/top/dv/LISTest/uart_rx.v b/cargo/top/dv/LISTest/uart_rx.v
new file mode 100644
index 0000000..6c50c57
--- /dev/null
+++ b/cargo/top/dv/LISTest/uart_rx.v
@@ -0,0 +1,136 @@
+module uart_rx #(
+    parameter CLKS_PER_BIT = 174
+)(
+   input        i_Clock,
+   input        i_Rx_Serial,
+   output       o_Rx_DV,
+   output [7:0] o_Rx_Byte
+   );
+    
+  parameter s_IDLE         = 3'b000;
+  parameter s_RX_START_BIT = 3'b001;
+  parameter s_RX_DATA_BITS = 3'b010;
+  parameter s_RX_STOP_BIT  = 3'b011;
+  parameter s_CLEANUP      = 3'b100;
+   
+  reg           r_Rx_Data_R = 1'b1;
+  reg           r_Rx_Data   = 1'b1;
+   
+  reg [7:0]     r_Clock_Count = 0;
+  reg [2:0]     r_Bit_Index   = 0; //8 bits total
+  reg [7:0]     r_Rx_Byte     = 0;
+  reg           r_Rx_DV       = 0;
+  reg [2:0]     r_SM_Main     = 0;
+   
+  // Purpose: Double-register the incoming data.
+  // This allows it to be used in the UART RX Clock Domain.
+  // (It removes problems caused by metastability)
+  always @(posedge i_Clock)
+    begin
+      r_Rx_Data_R <= i_Rx_Serial;
+      r_Rx_Data   <= r_Rx_Data_R;
+    end
+   
+   
+  // Purpose: Control RX state machine
+  always @(posedge i_Clock)
+    begin
+       
+      case (r_SM_Main)
+        s_IDLE :
+          begin
+            r_Rx_DV       <= 1'b0;
+            r_Clock_Count <= 0;
+            r_Bit_Index   <= 0;
+             
+            if (r_Rx_Data == 1'b0)          // Start bit detected
+              r_SM_Main <= s_RX_START_BIT;
+            else
+              r_SM_Main <= s_IDLE;
+          end
+         
+        // Check middle of start bit to make sure it's still low
+        s_RX_START_BIT :
+          begin
+            if (r_Clock_Count == (CLKS_PER_BIT-1)/2)
+              begin
+                if (r_Rx_Data == 1'b0)
+                  begin
+                    r_Clock_Count <= 0;  // reset counter, found the middle
+                    r_SM_Main     <= s_RX_DATA_BITS;
+                  end
+                else
+                  r_SM_Main <= s_IDLE;
+              end
+            else
+              begin
+                r_Clock_Count <= r_Clock_Count + 1;
+                r_SM_Main     <= s_RX_START_BIT;
+              end
+          end // case: s_RX_START_BIT
+         
+         
+        // Wait CLKS_PER_BIT-1 clock cycles to sample serial data
+        s_RX_DATA_BITS :
+          begin
+            if (r_Clock_Count < CLKS_PER_BIT-1)
+              begin
+                r_Clock_Count <= r_Clock_Count + 1;
+                r_SM_Main     <= s_RX_DATA_BITS;
+              end
+            else
+              begin
+                r_Clock_Count          <= 0;
+                r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
+                 
+                // Check if we have received all bits
+                if (r_Bit_Index < 7)
+                  begin
+                    r_Bit_Index <= r_Bit_Index + 1;
+                    r_SM_Main   <= s_RX_DATA_BITS;
+                  end
+                else
+                  begin
+                    r_Bit_Index <= 0;
+                    r_SM_Main   <= s_RX_STOP_BIT;
+                  end
+              end
+          end // case: s_RX_DATA_BITS
+     
+     
+        // Receive Stop bit.  Stop bit = 1
+        s_RX_STOP_BIT :
+          begin
+            // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
+            if (r_Clock_Count < CLKS_PER_BIT-1)
+              begin
+                r_Clock_Count <= r_Clock_Count + 1;
+                r_SM_Main     <= s_RX_STOP_BIT;
+              end
+            else
+              begin
+                r_Rx_DV       <= 1'b1;
+                r_Clock_Count <= 0;
+                r_SM_Main     <= s_CLEANUP;
+              end
+          end // case: s_RX_STOP_BIT
+     
+         
+        // Stay here 1 clock
+        s_CLEANUP :
+          begin
+            r_SM_Main <= s_IDLE;
+            r_Rx_DV   <= 1'b0;
+          end
+         
+         
+        default :
+          r_SM_Main <= s_IDLE;
+         
+      endcase
+    end   
+   
+  assign o_Rx_DV   = r_Rx_DV;
+  assign o_Rx_Byte = r_Rx_Byte;
+   
+endmodule // uart_rx
\ No newline at end of file
diff --git a/cargo/top/dv/LISTest/uart_tx.v b/cargo/top/dv/LISTest/uart_tx.v
new file mode 100644
index 0000000..2aec756
--- /dev/null
+++ b/cargo/top/dv/LISTest/uart_tx.v
@@ -0,0 +1,133 @@
+module uart_tx 
+  #(parameter CLKS_PER_BIT)
+  (
+   input       i_Clock,
+   input       i_Tx_DV,
+   input [7:0] i_Tx_Byte, 
+   output      o_Tx_Active,
+   output reg  o_Tx_Serial,
+   output      o_Tx_Done
+   );
+  
+  parameter s_IDLE         = 3'b000;
+  parameter s_TX_START_BIT = 3'b001;
+  parameter s_TX_DATA_BITS = 3'b010;
+  parameter s_TX_STOP_BIT  = 3'b011;
+  parameter s_CLEANUP      = 3'b100;
+   
+  reg [2:0]    r_SM_Main     = 0;
+  reg [7:0]    r_Clock_Count = 0;
+  reg [2:0]    r_Bit_Index   = 0;
+  reg [7:0]    r_Tx_Data     = 0;
+  reg          r_Tx_Done     = 0;
+  reg          r_Tx_Active   = 0;
+     
+  always @(posedge i_Clock)
+    begin
+       
+      case (r_SM_Main)
+        s_IDLE :
+          begin
+            o_Tx_Serial   <= 1'b1;         // Drive Line High for Idle
+            r_Tx_Done     <= 1'b0;
+            r_Clock_Count <= 0;
+            r_Bit_Index   <= 0;
+             
+            if (i_Tx_DV == 1'b1)
+              begin
+                r_Tx_Active <= 1'b1;
+                r_Tx_Data   <= i_Tx_Byte;
+                r_SM_Main   <= s_TX_START_BIT;
+              end
+            else
+              r_SM_Main <= s_IDLE;
+          end // case: s_IDLE
+         
+         
+        // Send out Start Bit. Start bit = 0
+        s_TX_START_BIT :
+          begin
+            o_Tx_Serial <= 1'b0;
+             
+            // Wait CLKS_PER_BIT-1 clock cycles for start bit to finish
+            if (r_Clock_Count < CLKS_PER_BIT-1)
+              begin
+                r_Clock_Count <= r_Clock_Count + 1;
+                r_SM_Main     <= s_TX_START_BIT;
+              end
+            else
+              begin
+                r_Clock_Count <= 0;
+                r_SM_Main     <= s_TX_DATA_BITS;
+              end
+          end // case: s_TX_START_BIT
+         
+         
+        // Wait CLKS_PER_BIT-1 clock cycles for data bits to finish         
+        s_TX_DATA_BITS :
+          begin
+            o_Tx_Serial <= r_Tx_Data[r_Bit_Index];
+             
+            if (r_Clock_Count < CLKS_PER_BIT-1)
+              begin
+                r_Clock_Count <= r_Clock_Count + 1;
+                r_SM_Main     <= s_TX_DATA_BITS;
+              end
+            else
+              begin
+                r_Clock_Count <= 0;
+                 
+                // Check if we have sent out all bits
+                if (r_Bit_Index < 7)
+                  begin
+                    r_Bit_Index <= r_Bit_Index + 1;
+                    r_SM_Main   <= s_TX_DATA_BITS;
+                  end
+                else
+                  begin
+                    r_Bit_Index <= 0;
+                    r_SM_Main   <= s_TX_STOP_BIT;
+                  end
+              end
+          end // case: s_TX_DATA_BITS
+         
+         
+        // Send out Stop bit.  Stop bit = 1
+        s_TX_STOP_BIT :
+          begin
+            o_Tx_Serial <= 1'b1;
+             
+            // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
+            if (r_Clock_Count < CLKS_PER_BIT-1)
+              begin
+                r_Clock_Count <= r_Clock_Count + 1;
+                r_SM_Main     <= s_TX_STOP_BIT;
+              end
+            else
+              begin
+                r_Tx_Done     <= 1'b1;
+                r_Clock_Count <= 0;
+                r_SM_Main     <= s_CLEANUP;
+                r_Tx_Active   <= 1'b0;
+              end
+          end // case: s_Tx_STOP_BIT
+         
+         
+        // Stay here 1 clock
+        s_CLEANUP :
+          begin
+            r_Tx_Done <= 1'b1;
+            r_SM_Main <= s_IDLE;
+          end
+         
+         
+        default :
+          r_SM_Main <= s_IDLE;
+         
+      endcase
+    end
+ 
+  assign o_Tx_Active = r_Tx_Active;
+  assign o_Tx_Done   = r_Tx_Done;
+   
+endmodule
\ No newline at end of file
diff --git a/cargo/top/rtl/LISTest/user_proj_example.v b/cargo/top/rtl/LISTest/user_proj_example.v
new file mode 100644
index 0000000..fac11b2
--- /dev/null
+++ b/cargo/top/rtl/LISTest/user_proj_example.v
@@ -0,0 +1,288 @@
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * LISTest
+ *
+ *-------------------------------------------------------------
+ */
+
+`ifdef SIM
+`include "wbm2axisp.v"
+`include "skidbuffer.v"
+`include "LISTest.v"
+`include "plusarg_reader.v"
+`endif
+
+module user_proj_example (
+`ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oen,
+
+    // IOs
+    input  [`MPRJ_IO_PADS-1:0] io_in,
+    output [`MPRJ_IO_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-1:0] io_oeb
+);
+
+// Logic Analyzer Signals
+    wire [127:0] la_data_in;
+    wire [127:0] la_data_out;
+    wire [127:0] la_oen;
+
+// IOs
+    wire [`MPRJ_IO_PADS-1:0] io_in;
+    wire [`MPRJ_IO_PADS-1:0] io_out;
+    wire [`MPRJ_IO_PADS-1:0] io_oeb;
+
+// AXI write address channel signals
+	wire 		w_o_axi_awvalid;	// Write address valid
+	wire 		w_i_axi_awready; 	// Slave is ready to accept
+	wire 		w_o_axi_awid;		// Write ID
+	wire [33:0] w_o_axi_awaddr;		// Write address
+	wire [7:0]  w_o_axi_awlen;		// Write Burst Length
+	wire [2:0]  w_o_axi_awsize;		// Write Burst size
+	wire [1:0]  w_o_axi_awburst;	// Write Burst type
+	wire [0:0]  w_o_axi_awlock;		// Write lock type
+	wire [3:0]  w_o_axi_awcache;	// Write Cache type
+	wire [2:0]  w_o_axi_awprot;		// Write Protection type
+	wire [3:0]  w_o_axi_awqos;		// Write Quality of Svc
+// AXI write data channel signals
+	wire 		w_o_axi_wvalid;		// Write valid
+	wire 		w_i_axi_wready;  	// Write data ready
+	wire [31:0]	w_o_axi_wdata;		// Write data
+	wire [3:0]  w_o_axi_wstrb;		// Write strobes
+	wire 		w_o_axi_wlast;		// Last write transaction
+// AXI write response channel signals
+ 	wire 		w_i_axi_bvalid;		// Write reponse valid
+	wire 		w_o_axi_bready;  	// Response ready
+	wire 		w_i_axi_bid;		// Response ID
+	wire [1:0]  w_i_axi_bresp;		// Write response
+// AXI read address channel signals
+	wire        w_o_axi_arvalid;	// Read address valid
+	wire        w_i_axi_arready;	// Read address ready
+	wire [0:0]  w_o_axi_arid;		// Read ID
+	wire [33:0]	w_o_axi_araddr;		// Read address
+	wire [7:0]  w_o_axi_arlen;		// Read Burst Length
+	wire [2:0]  w_o_axi_arsize;		// Read Burst size
+	wire [1:0]  w_o_axi_arburst;	// Read Burst type
+	wire [0:0]  w_o_axi_arlock;		// Read lock type
+	wire [3:0]  w_o_axi_arcache;	// Read Cache type
+	wire [2:0]  w_o_axi_arprot;		// Read Protection type
+	wire [3:0]  w_o_axi_arqos;		// Read Protection type
+// AXI read data channel signals
+	wire 		w_i_axi_rvalid;  	// Read reponse valid
+	wire 		w_o_axi_rready;  	// Read Response ready
+	wire [0:0] 	w_i_axi_rid;     	// Response ID
+	wire [31:0] w_i_axi_rdata;    	// Read data
+	wire [1:0]  w_i_axi_rresp;   	// Read response
+	wire 		w_i_axi_rlast;    	// Read last
+
+// Wires for inStream and outStream
+	wire 	   w_inStream_ready;
+	wire 	   w_inStream_valid;
+	wire [7:0] w_inStream_data;
+	wire 	   w_inStream_last;
+
+	wire 	   w_outStream_ready;
+	wire 	   w_outStream_valid;
+	wire [7:0] w_outStream_data;
+	wire 	   w_outStream_last;
+
+// Wires for uart
+	wire w_uart_int;
+	wire w_uart_tx;
+	wire w_uart_rx;
+
+// Assign inStream signals
+	genvar i;
+
+	assign io_oeb[0]    = 1'b0;    //fix pin to output
+	assign io_oeb[10:1] = 10'h3ff; //fix pins to inputs
+
+	assign io_out[10:1] = 10'h333; // drive unused outputs
+
+	assign io_out[0] 			= w_inStream_ready;
+	assign w_inStream_valid  	= io_in[1];
+	assign w_inStream_data[7:0] = io_in[9:2];
+	assign w_inStream_last 		= io_in[10];
+
+// Assign outStream signals
+	assign io_oeb[11]    = 1'b1;    // fix pin to input
+	assign io_oeb[21:12] = 10'h000; // fix pins to outputs
+
+	assign io_out[11]    = 1'b1;	// drive unused outputs  
+
+	assign w_outStream_ready = io_in[11];
+	assign io_out[12]        = w_outStream_valid;
+	assign io_out[20:13] 	 = w_outStream_data[7:0];
+	assign io_out[21]    	 = w_outStream_last;
+
+// set uart pins
+	assign io_oeb[22] = 1'b0;		// uart_int is output
+	assign io_out[22] = w_uart_int;
+	assign io_oeb[23] = 1'b0;		// uart_tx is output
+	assign io_out[23] = w_uart_tx;
+	assign io_out[24] = 1'b0;		
+	assign io_oeb[24] = 1'b1;		// uart_rx is input
+	assign w_uart_rx  = io_in[24];
+
+// Drive remaining io pins
+	assign io_out[`MPRJ_IO_PADS-1:25] = 13'h1666;
+	assign io_oeb[`MPRJ_IO_PADS-1:25] = 13'h0000;
+
+// Drive LA with zeroes
+	assign la_data_out = {128{1'b0}};
+
+// Wishbone to AXI4
+	wbm2axisp #(
+		.C_AXI_DATA_WIDTH(32),	// Width of the AXI R&W data
+		.C_AXI_ADDR_WIDTH(34),	// AXI Address width (log wordsize)
+		.C_AXI_ID_WIDTH(1),
+		.DW(32),				// Wishbone data width
+		.AW(32),   				// Wishbone address width (log wordsize)
+		.AXI_WRITE_ID(1'b0),
+		.AXI_READ_ID(1'b0)
+	) wb2axi (
+		.i_clk(wb_clk_i),						// System clock
+		.i_reset(wb_rst_i),					// Reset signal,drives AXI rst
+	// AXI write address channel signals
+		.o_axi_awvalid(w_o_axi_awvalid),	// Write address valid
+		.i_axi_awready(w_i_axi_awready), 	// Slave is ready to accept
+		.o_axi_awid(w_o_axi_awid),			// Write ID [C_AXI_ID_WIDTH-1:0]	
+		.o_axi_awaddr(w_o_axi_awaddr),		// Write address [C_AXI_ADDR_WIDTH-1:0]	
+		.o_axi_awlen(w_o_axi_awlen),		// Write Burst Length [7:0]		
+		.o_axi_awsize(w_o_axi_awsize),		// Write Burst size [2:0]		
+		.o_axi_awburst(w_o_axi_awburst),	// Write Burst type [1:0]		
+		.o_axi_awlock(w_o_axi_awlock),		// Write lock type [0:0]		
+		.o_axi_awcache(w_o_axi_awcache),	// Write Cache type [3:0]		
+		.o_axi_awprot(w_o_axi_awprot),		// Write Protection type [2:0]		
+		.o_axi_awqos(w_o_axi_awqos),		// Write Quality of Svc [3:0]		
+	// AXI write data channel signals
+		.o_axi_wvalid(w_o_axi_wvalid),		// Write valid
+		.i_axi_wready(w_i_axi_wready),  	// Write data ready
+		.o_axi_wdata(w_o_axi_wdata),		// Write data [C_AXI_DATA_WIDTH-1:0]	
+		.o_axi_wstrb(w_o_axi_wstrb),		// Write strobes [C_AXI_DATA_WIDTH/8-1:0] 
+		.o_axi_wlast(w_o_axi_wlast),		// Last write transaction
+	// AXI write response channel signals
+		.i_axi_bvalid(w_i_axi_bvalid),  	// Write reponse valid
+		.o_axi_bready(w_o_axi_bready),  	// Response ready
+		.i_axi_bid(w_i_axi_bid),			// Response ID [C_AXI_ID_WIDTH-1:0]	
+		.i_axi_bresp(w_i_axi_bresp),		// Write response [1:0]		
+	// AXI read address channel signals
+		.o_axi_arvalid(w_o_axi_arvalid),	// Read address valid
+		.i_axi_arready(w_i_axi_arready),	// Read address ready
+		.o_axi_arid(w_o_axi_arid),			// Read ID [C_AXI_ID_WIDTH-1:0]	
+		.o_axi_araddr(w_o_axi_araddr),		// Read address [C_AXI_ADDR_WIDTH-1:0]	
+		.o_axi_arlen(w_o_axi_arlen),		// Read Burst Length [7:0]		
+		.o_axi_arsize(w_o_axi_arsize),		// Read Burst size [2:0]		
+		.o_axi_arburst(w_o_axi_arburst),	// Read Burst type [1:0]		
+		.o_axi_arlock(w_o_axi_arlock),		// Read lock type [0:0]		
+		.o_axi_arcache(w_o_axi_arcache),	// Read Cache type [3:0]		
+		.o_axi_arprot(w_o_axi_arprot),		// Read Protection type [2:0]		
+		.o_axi_arqos(w_o_axi_arqos),		// Read Protection type [3:0]		
+	// AXI read data channel signals
+		.i_axi_rvalid(w_i_axi_rvalid),  	// Read reponse valid
+		.o_axi_rready(w_o_axi_rready),  	// Read Response ready
+		.i_axi_rid(w_i_axi_rid),     		// Response ID [C_AXI_ID_WIDTH-1:0]	
+		.i_axi_rdata(w_i_axi_rdata),   		// Read data [C_AXI_DATA_WIDTH-1:0] 
+		.i_axi_rresp(w_i_axi_rresp),   		// Read response [1:0]		
+		.i_axi_rlast(w_i_axi_rlast),   		// Read last
+	// We'll share the clock and the reset
+		.i_wb_cyc(wbs_cyc_i),
+		.i_wb_stb(wbs_stb_i),
+		.i_wb_we(wbs_we_i),
+		.i_wb_addr(wbs_adr_i),     // [(AW-1):0]
+		.i_wb_data(wbs_dat_i),     // [(DW-1):0]
+		.i_wb_sel(wbs_sel_i),      // [(DW/8-1):0]
+		.o_wb_stall(),
+		.o_wb_ack(wbs_ack_o),
+		.o_wb_data(wbs_dat_o), // [(DW-1):0]
+		.o_wb_err()
+	);
+
+// LIS
+	LISTest lis (
+		.clock(wb_clk_i),
+		.reset(wb_rst_i),
+	// AXI write address channel signals
+		.ioMem_0_aw_ready(w_i_axi_awready),
+		.ioMem_0_aw_valid(w_o_axi_awvalid),
+		.ioMem_0_aw_bits_id(w_o_axi_awid),
+		.ioMem_0_aw_bits_addr(w_o_axi_awaddr[33:2]),//[31:0]
+		.ioMem_0_aw_bits_len(w_o_axi_awlen), 		// [7:0]  
+		.ioMem_0_aw_bits_size(w_o_axi_awsize), 		// [2:0]  
+		.ioMem_0_aw_bits_burst(w_o_axi_awburst), 	// [1:0]  
+		.ioMem_0_aw_bits_lock(w_o_axi_awlock),
+		.ioMem_0_aw_bits_cache(w_o_axi_awcache), 	// [3:0]  
+		.ioMem_0_aw_bits_prot(w_o_axi_awprot), 		// [2:0]  
+		.ioMem_0_aw_bits_qos(w_o_axi_awqos), 		// [3:0]  
+	// AXI write data channel signals
+		.ioMem_0_w_ready(w_i_axi_wready),
+		.ioMem_0_w_valid(w_o_axi_wvalid),
+		.ioMem_0_w_bits_data(w_o_axi_wdata), 		// [31:0] 
+		.ioMem_0_w_bits_strb(w_o_axi_wstrb), 		// [3:0]  
+		.ioMem_0_w_bits_last(w_o_axi_wlast),
+	// AXI write response channel signals
+		.ioMem_0_b_ready(w_o_axi_bready),
+		.ioMem_0_b_valid(w_i_axi_bvalid),
+		.ioMem_0_b_bits_id(w_i_axi_bid),
+		.ioMem_0_b_bits_resp(w_i_axi_bresp), 		// [1:0] 
+	// AXI read address channel signals
+		.ioMem_0_ar_ready(w_i_axi_arready),
+		.ioMem_0_ar_valid(w_o_axi_arvalid),
+		.ioMem_0_ar_bits_id(w_o_axi_arid),
+		.ioMem_0_ar_bits_addr(w_o_axi_araddr[33:2]),// [31:0] 
+		.ioMem_0_ar_bits_len(w_o_axi_arlen), 		// [7:0]  
+		.ioMem_0_ar_bits_size(w_o_axi_arsize), 		// [2:0]  
+		.ioMem_0_ar_bits_burst(w_o_axi_arburst), 	// [1:0]  
+		.ioMem_0_ar_bits_lock(w_o_axi_arlock),
+		.ioMem_0_ar_bits_cache(w_o_axi_arcache), 	// [3:0]  
+		.ioMem_0_ar_bits_prot(w_o_axi_arprot), 		// [2:0]  
+		.ioMem_0_ar_bits_qos(w_o_axi_arqos), 		// [3:0]  
+	// AXI read data channel signals
+		.ioMem_0_r_ready(w_o_axi_rready),
+		.ioMem_0_r_valid(w_i_axi_rvalid),
+		.ioMem_0_r_bits_id(w_i_axi_rid),
+		.ioMem_0_r_bits_data(w_i_axi_rdata), 		// [31:0] 
+		.ioMem_0_r_bits_resp(w_i_axi_rresp), 		// [1:0]  
+		.ioMem_0_r_bits_last(w_i_axi_rlast),
+	// AXI-stream
+        .inStream_0_ready(w_inStream_ready),
+  		.inStream_0_valid(w_inStream_valid),
+  		.inStream_0_bits_data(w_inStream_data),
+  		.inStream_0_bits_last(w_inStream_last),
+		.outStream_0_ready(w_outStream_ready),
+  		.outStream_0_valid(w_outStream_valid),
+  		.outStream_0_bits_data(w_outStream_data),
+  		.outStream_0_bits_last(w_outStream_last),
+        .int_0(w_uart_int),
+        .uTx(w_uart_tx),
+        .uRx(w_uart_rx)
+	);
+endmodule
+`default_nettype wire
\ No newline at end of file
diff --git a/cargo/wb2axip b/cargo/wb2axip
new file mode 160000
index 0000000..e80d7a6
--- /dev/null
+++ b/cargo/wb2axip
@@ -0,0 +1 @@
+Subproject commit e80d7a6b5cab0a4073fd8c9037737231748bdaee
diff --git a/info.yaml b/info.yaml
index 685ee5e..feae5f1 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,18 +1,16 @@
 --- 
 project: 
-  description: "A template SoC for Google sponsored Open MPW shuttles for SKY130."
+  description: "A digital linear insertion sorter accelerator."
   foundry: "SkyWater"
-  git_url: "https://github.com/efabless/caravel.git"
-  organization: "Efabless"
-  organization_url: "http://efabless.com"
-  owner: "Tim Edwards"
+  git_url: "https://github.com/elektrotehnika/caravel_linsorter.git"
+  organization: "elektrotehnika"
+  organization_url: "elektrotehnika.github.io"
+  owner: "Vladimir Milovanović"
   process: "SKY130"
-  project_name: "Caravel"
-  tags: 
-    - "Open MPW"
-    - "Test Harness"
-  category: "Test Harness"
+  project_name: "linsorter"
+  tags: "Open MPW"
+  category: "Accelerator"
   top_level_netlist: "verilog/gl/caravel.v"
   user_level_netlist: "verilog/gl/user_project_wrapper.v"
   version: "1.00"
-  cover_image: "doc/ciic_harness.png"
+  cover_image: "cargo/doc/images/LinearSorters.png"