diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 130a35c..10c054a 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -622,16 +622,20 @@
     user_id_programming #(
 	.USER_PROJECT_ID(USER_PROJECT_ID)
     ) user_id_value (
+`ifdef USE_POWER_PINS
 	.vdd1v8(vccd),
 	.vss(vssd),
+`endif
 	.mask_rev(mask_rev)
     );
 
     // Power-on-reset circuit
     simple_por por (
+`ifdef USE_POWER_PINS
 		.vdd3v3(vddio),
 		.vdd1v8(vccd),
 		.vss(vssio),
+`endif
 		.porb_h(porb_h),
 		.porb_l(porb_l),
 		.por_l(por_l)
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index f04fa5c..7fef90d 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -2,9 +2,11 @@
 `timescale 1 ns / 1 ps
 
 module simple_por(
+`ifdef USE_POWER_PINS
     inout vdd3v3,
     inout vdd1v8,
     inout vss,
+`endif
     output porb_h,
     output porb_l,
     output por_l
diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index 526a802..934f9d7 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -7,8 +7,10 @@
 module user_id_programming #(
     parameter [ 0:0] USER_PROJECT_ID = 32'h0
 ) (
+`ifdef USE_POWER_PINS
     inout vdd1v8,
     inout vss,
+`endif
     output [31:0] mask_rev
 );
     wire [31:0] mask_rev;