)]}'
{
  "commit": "d01c63748cd1b4f3b3201504f6d858936a5cd348",
  "tree": "0d76f16f945d7c9139e961fa03e5f87228b0e670",
  "parents": [
    "22d29d6e8973054c55f7832e248749a36388bd27"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed Oct 28 13:40:03 2020 -0400"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Oct 28 22:58:29 2020 +0200"
  },
  "message": "Modified the mprj_ctrl.v verilog to be completely clear about how\nmany bits are set to zero for each of the contributers to the\niomem_rdata_pre vector.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4255a9b9a06baa4b801e7369a6eac1ddc020b141",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer2/Makefile",
      "new_id": "3feaad758ea8f26b414136bfb78e97c14ed0ffdc",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer2/Makefile"
    },
    {
      "type": "modify",
      "old_id": "0f385de928e657af81b5c1e9a54b4c846a48f453",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mprj_ctrl.v",
      "new_id": "5ca05539d2f6d6e8dc69862f01e752567f04ef48",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mprj_ctrl.v"
    }
  ]
}