)]}'
{
  "commit": "ca2f318bb428801e0739cc341d80def2d8c70559",
  "tree": "e3893a840869be501ecd824b809615bae1bc67da",
  "parents": [
    "f51dd08a1f4716df0cca0a0ebe28f99544cc611c"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Tue Oct 06 10:05:11 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Tue Oct 06 10:05:11 2020 -0400"
  },
  "message": "Various corrections to simplify the user project I/O wiring\nconnections into the management area.  Corrected testbenches\nfor hkspi, mem, uart, perf, and gpio.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ac5dfdf81f9355c5525cf7e13e058d0457e99c25",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/defs.h",
      "new_id": "660b103f5607ad59046ca3642641071bf6373937",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/defs.h"
    },
    {
      "type": "modify",
      "old_id": "31a859c68905c49f3267f1cd8bc551a14e4365c8",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/hkspi/Makefile",
      "new_id": "b3930e2b305329bd17dee97e2f008a1b781849c1",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/hkspi/Makefile"
    },
    {
      "type": "modify",
      "old_id": "a41521471560a6400045261b945e25ab0aee06e2",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c",
      "new_id": "03cb7f55656f64afc593950344e9596fdba6acac",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c"
    },
    {
      "type": "modify",
      "old_id": "13677f7c2e539c61b7b8158380ffc4ccb65f39cd",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v",
      "new_id": "d13918267ce10835c74a20dfc682540800c0faa5",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v"
    },
    {
      "type": "modify",
      "old_id": "31d0f7529e4f34eb08c3776b15f3f79042b235aa",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/mem/mem.c",
      "new_id": "8f4b5423d034de4e40be8ecd64d6acdc86faf226",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/mem/mem.c"
    },
    {
      "type": "modify",
      "old_id": "5248cd738cec627ce6063ef8e6747ce985a5ef94",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/mem/mem_tb.v",
      "new_id": "d815b9ddb24c9b091767be26f8c873a31ecc4616",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/mem/mem_tb.v"
    },
    {
      "type": "modify",
      "old_id": "bd94f5df81e8edb283d5f7e74f8692708105cb44",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/perf/perf.c",
      "new_id": "b0edcb9eb428adf2bbb674d2e239192f2382afb6",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/perf/perf.c"
    },
    {
      "type": "modify",
      "old_id": "61a044de01314b90b726c5f6b2d96d9eb64548b3",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/perf/perf_tb.v",
      "new_id": "985ca3ff4ebf959c153225eff0a4df222160633e",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/perf/perf_tb.v"
    },
    {
      "type": "modify",
      "old_id": "bd4b67de44f2c0d2d870ec6470b8855ad11f65fc",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/uart/uart.c",
      "new_id": "a0b5cc34152356251998164d982f903d37f79000",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/uart/uart.c"
    },
    {
      "type": "modify",
      "old_id": "4f879fe33f24909cae9ff57f67b02ca5f4412550",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/uart/uart_tb.v",
      "new_id": "425ef1e8b46078ceb25d4fe77182689dfb73c254",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/uart/uart_tb.v"
    },
    {
      "type": "modify",
      "old_id": "58dd69275e3c66e9ca549a14494902fd13d2c7e6",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "a39fdeaa5517996154798269e36c7a28158808b3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "97bd7a11c73c20e692814f7885962cd493947220",
      "old_mode": 33188,
      "old_path": "verilog/rtl/housekeeping_spi.v",
      "new_id": "0a1cce683953881bc9b8b47d4bf3ff52d671a53a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/housekeeping_spi.v"
    },
    {
      "type": "modify",
      "old_id": "e6b837be05933c9fb173875a874014fa2ea3984b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_core.v",
      "new_id": "032d2f53d72c1872bd4651e0ebcbe1e62ff56212",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_core.v"
    },
    {
      "type": "modify",
      "old_id": "ce43250d372ea910357272773e445c0be437747d",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_soc.v",
      "new_id": "0de30f218c4f720d80299042d1a248cf654970ac",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_soc.v"
    },
    {
      "type": "modify",
      "old_id": "035e756f547122dccc2a542eeb53bba2b2e788f6",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mprj_ctrl.v",
      "new_id": "117fcfea5de789cc35ef370950fdd2541adb1fe9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mprj_ctrl.v"
    },
    {
      "type": "modify",
      "old_id": "dad5471f6e1c68ff717df0793bf0b341924110c8",
      "old_mode": 33261,
      "old_path": "verilog/rtl/simple_spi_master.v",
      "new_id": "a2a33b671edb95ac3f1aedf57c2fce2a460eba68",
      "new_mode": 33261,
      "new_path": "verilog/rtl/simple_spi_master.v"
    },
    {
      "type": "modify",
      "old_id": "51e95c787ee18c8d35222889f3d746129d980652",
      "old_mode": 33188,
      "old_path": "verilog/rtl/simpleuart.v",
      "new_id": "54a3cb4e59023ebea30af9b4e0c12362dddb7566",
      "new_mode": 33188,
      "new_path": "verilog/rtl/simpleuart.v"
    }
  ]
}
