)]}'
{
  "commit": "bd9ffeaaee6a52c05133427c84a1c42c363b9200",
  "tree": "afd95241c613102ea74337515a9d1bef2aa7cadb",
  "parents": [
    "3e94501e51850deff5cbcfe4904b1401c86e64b1"
  ],
  "author": {
    "name": "Mohamed Shalan",
    "email": "mshalan@aucegypt.edu",
    "time": "Fri Jan 08 20:49:00 2021 +0200"
  },
  "committer": {
    "name": "Mohamed Shalan",
    "email": "mshalan@aucegypt.edu",
    "time": "Fri Jan 08 20:49:00 2021 +0200"
  },
  "message": "Updated layout\n\n- wrapper lvs \u0026 magic clean\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "fc74db550fe92240536402c09aeb47e52b02b39e",
      "old_mode": 33188,
      "old_path": "Makefile",
      "new_id": "8bac20f6549b666583aff0ff8cfa697fae83a325",
      "new_mode": 33188,
      "new_path": "Makefile"
    },
    {
      "type": "modify",
      "old_id": "cff8a08f7ef9f7b9a3349c4812cd4de4c02e8f2c",
      "old_mode": 33188,
      "old_path": "def/user_project_wrapper.def",
      "new_id": "51736f82eba8ad32a6f6c3f279036e8e6d36f73c",
      "new_mode": 33188,
      "new_path": "def/user_project_wrapper.def"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "2fee0c4641cabd688babbf068d41ab346f9582a3",
      "new_mode": 33188,
      "new_path": "doc/gds.png"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "6615814fcf348e36906585dfaab968d2d1df3eb2",
      "new_mode": 33188,
      "new_path": "gds/caravel.gds.gz.00.split"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "582d3b2730f248df75bf4114d66ff17211092f73",
      "new_mode": 33188,
      "new_path": "gds/caravel.gds.gz.01.split"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "f96dded5850851e890cd4666d6b46f4fbd813eca",
      "new_mode": 33188,
      "new_path": "gds/caravel.mag"
    },
    {
      "type": "rename",
      "old_id": "d729e240f4d7039ed85d599965ebf90bd73bcbe8",
      "old_mode": 33188,
      "old_path": "gds/caravel.gds.gz",
      "new_id": "d729e240f4d7039ed85d599965ebf90bd73bcbe8",
      "new_mode": 33188,
      "new_path": "gds/caravel.old.gds.gz",
      "score": 100
    },
    {
      "type": "modify",
      "old_id": "6db064413f05e08a6c9e4b85458e04dc105cfd1b",
      "old_mode": 33188,
      "old_path": "gds/user_project_wrapper.gds.gz",
      "new_id": "264bb0e9e3163e65a402e24f78039ad26a255d8b",
      "new_mode": 33188,
      "new_path": "gds/user_project_wrapper.gds.gz"
    },
    {
      "type": "modify",
      "old_id": "7617c75ae6952863a9381a0e3765a2e2c12261d0",
      "old_mode": 33188,
      "old_path": "mag/user_project_wrapper.mag",
      "new_id": "5662afc9f9b6a834f0f0fb92a7b2bdc7a74fd762",
      "new_mode": 33188,
      "new_path": "mag/user_project_wrapper.mag"
    },
    {
      "type": "delete",
      "old_id": "968a74b46df9c0bc629bd54d747e40c63581c2dd",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test1/Makefile",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "9759ed739a2478391da2f78e3bdb632b48452c8d",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test1/la_test1.c",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "210098fd2daa1249d31de4e5d84e9c7c78d154ce",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "4980a080390009b9ad9b3e4014931b18acfa077e",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test2/Makefile",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "0267d252e5a02ccc98bb9c19d3bc82f93ef2e70a",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test2/la_test2.c",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "b9e5c806bbab20cfa1243a6d409900dc5dfd234a",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "446d614d5486eded4692c5b3afa14d794f62d7c6",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project/gl/DFFRAM_4K.v"
    },
    {
      "type": "modify",
      "old_id": "763904e5ec241a890220bd4f35589ba69c69d956",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_project/gl/DMC_32x16HC.v",
      "new_id": "4b878c3abcdc3f4d6605ad3587fdaff884d5647f",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project/gl/DMC_32x16HC.v"
    },
    {
      "type": "modify",
      "old_id": "1c59c8214479ce71cf7541cf2fab6f4db8c722ef",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_project/gl/NfiVe32_SYS.v",
      "new_id": "bf287d7250fec5d17857a1dd575fe9ee2161b1af",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project/gl/NfiVe32_SYS.v"
    },
    {
      "type": "modify",
      "old_id": "03a742dc443a6681aed8bcdb85f51d973b043619",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_project/gl/apb_sys_0.v",
      "new_id": "6d74fa0253bcfa0cfcb04df8580616668b8d5e38",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project/gl/apb_sys_0.v"
    },
    {
      "type": "modify",
      "old_id": "1f1938c10e81efa0aa3b030301bb7fcb32b09037",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_project/gl/user_project_wrapper.v",
      "new_id": "f0fa015130feebcfcb7c99a3d0b0586476ce628c",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project/gl/user_project_wrapper.v"
    },
    {
      "type": "modify",
      "old_id": "1f1938c10e81efa0aa3b030301bb7fcb32b09037",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_project_wrapper.v",
      "new_id": "f0fa015130feebcfcb7c99a3d0b0586476ce628c",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project_wrapper.v"
    },
    {
      "type": "modify",
      "old_id": "b655a1aa5825f11d23a271e042986807ec4c6f2f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project/AHB_sys_0/AHBlite_bus0.v",
      "new_id": "8c4a05836680db32d32079630dd1515993ee4613",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project/AHB_sys_0/AHBlite_bus0.v"
    },
    {
      "type": "modify",
      "old_id": "9b931cbabbd636c4354e4cd8d40d4132c1bd5fe9",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project/AHB_sys_0/AHBlite_sys_0.v",
      "new_id": "26295091b90f33b598926ec955e21471df8b9749",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project/AHB_sys_0/AHBlite_sys_0.v"
    },
    {
      "type": "modify",
      "old_id": "9b92832d093e64837ec57a9f9e930174a142a2be",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project/AHB_sys_0/APB_sys_0/APB_sys_0.v",
      "new_id": "efb894cb43326f7ded1d957e3301a5c0d4156759",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project/AHB_sys_0/APB_sys_0/APB_sys_0.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b88dd8279a59d51f0f3b6ec203c733fb07dfaa32",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project/IPs/DFFRAM_4K.v"
    },
    {
      "type": "modify",
      "old_id": "482902cff3ce9a5c35dc70f50d861b24f636fd58",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project/IPs/QSPI_XIP_CTRL.v",
      "new_id": "5e8eabcc9b976fa51fa7b8fa52c796617ab41c64",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project/IPs/QSPI_XIP_CTRL.v"
    },
    {
      "type": "modify",
      "old_id": "89c29acd68d8ed8b6c1d282f6526eb77e569a884",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project/IPs/RAM_3Kx32.v",
      "new_id": "f9dbc25531f3c484383c897c8ec21dc2c66e9e46",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project/IPs/RAM_3Kx32.v"
    },
    {
      "type": "modify",
      "old_id": "146ffa218a52b51902f78ce01c2869bcb7bde3a1",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project/IPs/RAM_4Kx32.v",
      "new_id": "8a9b17a53fb798c98494ca9695678cf093f8ccbd",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project/IPs/RAM_4Kx32.v"
    },
    {
      "type": "modify",
      "old_id": "97f06888174911acc8e97197ef70755b6925e29e",
      "old_mode": 33261,
      "old_path": "verilog/rtl/user_project/NfiVe32.v",
      "new_id": "91c457b037b502ca672dc58790c766ee20db5f00",
      "new_mode": 33261,
      "new_path": "verilog/rtl/user_project/NfiVe32.v"
    },
    {
      "type": "modify",
      "old_id": "bc7001606a14bddb2845f5c07ea6bc007fa69e36",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project/soc_core.v",
      "new_id": "f90690de444d95defc8b656afacd6c9c5a502535",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project/soc_core.v"
    },
    {
      "type": "modify",
      "old_id": "4ffde1544df4913495f7cb64016c4a3d263b3560",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project/user_project_wrapper.v",
      "new_id": "ff1bf9c10bed449750b882ee01af01f395aad8c3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project/user_project_wrapper.v"
    },
    {
      "type": "modify",
      "old_id": "4ffde1544df4913495f7cb64016c4a3d263b3560",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "ff1bf9c10bed449750b882ee01af01f395aad8c3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}