)]}'
{
  "commit": "7a8cbb17d982936bcf08ac4faabe7cbe6eda46be",
  "tree": "aa0db5554e024223e07a063b304b52251d6f2514",
  "parents": [
    "53d9218c9e1613c4616ca9d4f71195778520e66d"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Oct 12 11:32:11 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Oct 12 11:32:11 2020 -0400"
  },
  "message": "Added a secondary clock output, going to the user area, that is derived\nfrom the 90-degree phase PLL clock and run on an independent divider.\nThe use of the 90-degree phase clock is mostly to balance the output\nloads.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f0708d2e9906f62a63b0de3bdd7d14007f5bdc41",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "a73cf989e9fe317b82ea68151bdc15d9b3b1a697",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "db249d2b1d7e0dad3174e11eee7be4b40f910d2b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel_clocking.v",
      "new_id": "ecf82157e9ff8c665be46f6143b9863895bcedca",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel_clocking.v"
    },
    {
      "type": "modify",
      "old_id": "10ea1b34546a85fdc1e2015e7ab03855e276189b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/housekeeping_spi.v",
      "new_id": "2942b2744e6f5cc6dd8bc959e12717b98fcecaaf",
      "new_mode": 33188,
      "new_path": "verilog/rtl/housekeeping_spi.v"
    },
    {
      "type": "modify",
      "old_id": "8435a5e5d1059f5ff69a6c4d59360fa0a322c73f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_core.v",
      "new_id": "45f65a4bfbd2dedcf40a343e9ecd028fad90366e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_core.v"
    },
    {
      "type": "modify",
      "old_id": "24b9cbcb8f3b9b103168c8a26f50f727d1a31150",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_protect.v",
      "new_id": "1b04731f5ced201a1e05f782d9b749847e48a69b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_protect.v"
    }
  ]
}