diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index d802e86..068f2a2 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -36,8 +36,8 @@
     `define NO_HC_CACHE
     `include "DFFRAM_beh.v"
 `else
-    `include "user_project/IPs/DFFRAM.v"
-    `include "user_project/IPs/DFFRAMBB.v"
+    // `include "user_project/IPs/DFFRAM.v"
+    // `include "user_project/IPs/DFFRAMBB.v"
 `endif
 
 `include "user_project/AHB_sys_0/AHBlite_sys_0.v"
@@ -112,7 +112,7 @@
     // assign GPIOIN_Sys0_S2 = GPIO_PINS;
 
 	// Serial Terminal connected to UART0 TX*/
-    terminal term(.rx(mprj_io[22]));
+    terminal term(.rx(mprj_io[21]));  // RsTx_Sys0_SS0_S0
 
     // SPI SRAM connected to SPI0
     wire SPI_HOLD = 1'b1;
@@ -161,10 +161,6 @@
 		power4 <= 1'b1;
 	end
 
-	always @(mprj_io) begin
-		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
-	end
-
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
diff --git a/verilog/dv/caravel/user_proj_example/sw_n5/test.c b/verilog/dv/caravel/user_proj_example/sw_n5/test.c
index d48a2f1..e06b253 100644
--- a/verilog/dv/caravel/user_proj_example/sw_n5/test.c
+++ b/verilog/dv/caravel/user_proj_example/sw_n5/test.c
@@ -95,7 +95,6 @@
 
     // PWM
     uart_puts (0, "PWM Test: ", 10);
-    tmr_init(0, 100, 10);       // 1usec
     pwm_init(0, 250, 99, 5);
  	pwm_enable(0);
     DELAY(300);
@@ -106,41 +105,7 @@
     DELAY(400);
    
     // Done!
-    uart_puts(0, "Done!\n", 5);
+    uart_puts(0, "Done!\n ", 6);
+    DELAY(100);
     return 0;
-}
-
-/*
-
-    (unsigned int *)(0x49000000) = -20;
-    (unsigned int *)(0x49000004) = 50;
-    
-    int x = 10;
-    int y = 50;
-
-    int z = x * y;
-
-    x = fact(5);
-
-    gpio_write(x);
-
-    uart_init (0, 0);
-    uart_puts (0, "Hello World!\n", 13);
-
-    gpio_write(z);
-
-    for(int i=0; i<z; i++);
-
-    gpio_write(0x00AA);
-
-    x = 5;
-    //asm volatile ("csrrw   zero, mie, %0" :: "r" (x));
-    asm volatile ("csrrwi   zero, mie, %0" :: "i" (5));
-
-    x = 0x100;
-    asm volatile ("csrrw   zero, 0x310, %0" :: "r" (x));
-
-    gpio_im(0x0100);
-
-    for(int i=0; i<50; i++);
-    */
\ No newline at end of file
+}
\ No newline at end of file
diff --git a/verilog/rtl/user_project/rtl/IPs/DFFRAMBB.v b/verilog/rtl/user_project/rtl/IPs/DFFRAMBB.v
index 5599bc8..2825426 100644
--- a/verilog/rtl/user_project/rtl/IPs/DFFRAMBB.v
+++ b/verilog/rtl/user_project/rtl/IPs/DFFRAMBB.v
@@ -67,14 +67,46 @@
 endmodule
 
 module DEC2x4 (
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
     input           EN,
     input   [1:0]   A,
     output  [3:0]   SEL
 );
-    sky130_fd_sc_hd__nor3b_4    AND0 ( .Y(SEL[0]), .A(A[0]),   .B(A[1]), .C_N(EN) );
-    sky130_fd_sc_hd__and3b_4    AND1 ( .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) );
-    sky130_fd_sc_hd__and3b_4    AND2 ( .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) );
-    sky130_fd_sc_hd__and3_4     AND3 ( .X(SEL[3]), .A(A[1]),   .B(A[0]), .C(EN) );
+    sky130_fd_sc_hd__nor3b_4    AND0 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .Y(SEL[0]), .A(A[0]),   .B(A[1]), .C_N(EN) );
+    sky130_fd_sc_hd__and3b_4    AND1 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) );
+    sky130_fd_sc_hd__and3b_4    AND2 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) );
+    sky130_fd_sc_hd__and3_4     AND3 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[3]), .A(A[1]),   .B(A[0]), .C(EN) );
     
 endmodule
 
@@ -123,11 +155,22 @@
 endmodule
 
 module MUX4x1_32(
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
     input   [31:0]      A0, A1, A2, A3,
     input   [1:0]       S,
     output  [31:0]      X
 );
-    sky130_fd_sc_hd__mux4_1 MUX[31:0] (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) );
+    sky130_fd_sc_hd__mux4_1 MUX[31:0] (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) );
 endmodule
 
 module PASS (input [31:0] A, output [31:0] X);
diff --git a/verilog/rtl/user_project/rtl/IPs/RAM_3Kx32.v b/verilog/rtl/user_project/rtl/IPs/RAM_3Kx32.v
index 57f8fa5..d9d1125 100644
--- a/verilog/rtl/user_project/rtl/IPs/RAM_3Kx32.v
+++ b/verilog/rtl/user_project/rtl/IPs/RAM_3Kx32.v
@@ -2,6 +2,10 @@
 `default_nettype none
 
 module RAM_3Kx32 (
+`ifdef USE_POWER_PINS
+    VPWR,
+    VGND,
+`endif
     CLK,
     WE,
     EN,
@@ -41,9 +45,29 @@
         
     endgenerate 
     
-    MUX4x1_32 MUX ( .A0(_Do_[0]), .A1(_Do_[1]), .A2(_Do_[2]), .A3(32'b0), .S(A[11:10]), .X(Do_pre) );
-    DEC2x4 DEC ( .EN(EN), .A(A[11:10]), .SEL(_EN_) );
+    MUX4x1_32 MUX ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif
+        .A0(_Do_[0]), .A1(_Do_[1]), .A2(_Do_[2]), .A3(32'b0), .S(A[11:10]), .X(Do_pre) 
+    );
+    DEC2x4 DEC ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif
+        .EN(EN), .A(A[11:10]), .SEL(_EN_)
+    );
 
-    sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre));
+    sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(Do), .A(Do_pre)
+    );
     
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/user_project/rtl/soc_core.v b/verilog/rtl/user_project/rtl/soc_core.v
index 115fc2c..bc70016 100644
--- a/verilog/rtl/user_project/rtl/soc_core.v
+++ b/verilog/rtl/user_project/rtl/soc_core.v
@@ -3,6 +3,10 @@
 `timescale 1ns/1ns
 
 module soc_core (
+`ifdef USE_POWER_PINS
+	input VPWR,
+	input VGND,
+`endif
 	input HCLK, 
 	input HRESETn,
 	
@@ -182,6 +186,10 @@
 
 
 	RAM_3Kx32 RAM (
+	`ifdef USE_POWER_PINS
+		.VPWR(VPWR),
+		.VGND(VGND),
+	`endif
 		.CLK(HCLK),
 		.WE(SRAMWEN_Sys0_S1),
 		.EN(SRAMCS0_Sys0_S1),
diff --git a/verilog/rtl/user_project/rtl/user_project_wrapper.v b/verilog/rtl/user_project/rtl/user_project_wrapper.v
index caa1883..863412a 100644
--- a/verilog/rtl/user_project/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project/rtl/user_project_wrapper.v
@@ -121,6 +121,10 @@
     assign io_oeb[17:14] = {4{~fdoeb}};
 
     soc_core core(
+    `ifdef USE_POWER_PINS
+        .VPWR(vccd1),
+        .VGND(vssd1)
+    `endif
 
         .HCLK(wb_clk_i), 
 	    .HRESETn(~wb_rst_i),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index a0f87c7..65df046 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -121,6 +121,10 @@
     assign io_oeb[17:14] = {4{~fdoeb}};
 
     soc_core core(
+    `ifdef USE_POWER_PINS
+        .VPWR(vccd1),
+        .VGND(vssd1),
+    `endif
 
         .HCLK(wb_clk_i), 
 	    .HRESETn(la_data_in[9]),