)]}'
{
  "commit": "5ae07d9b4afeab093f9da812ec8cc29a1d800dbb",
  "tree": "2068a7ecbb70347a57d7aee6b66c77c4356fb193",
  "parents": [
    "9eda80dd074325b1d42354785b1aece24ce83017"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Oct 08 22:10:00 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Oct 08 22:10:00 2020 -0400"
  },
  "message": "Corrected the error causing the failure of the GPIO testbench.\nNow it only remains to update the other testbenches with the\ncorrect pin names for all the voltage domains.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "90f84008cc6ba18993a1096e55b55a9324aa68eb",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mprj_io.v",
      "new_id": "1c29d96c732fa09c28604610177637e085c2ab9b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mprj_io.v"
    }
  ]
}