../pdk/hd_primitives.v 
../pdk/hd_functional.v

../verilog/rtl/AHB_sys_0/AHBlite_sys_0.v 
../verilog/rtl/AHB_sys_0/AHBlite_bus0.v
../verilog/rtl/AHB_sys_0/AHBlite_GPIO.v
../verilog/rtl/AHB_sys_0/AHBlite_db_reg.v

#-y ../verilog/rtl/AHB_sys_0/APB_sys_0/
../verilog/rtl/AHB_sys_0/APB_sys_0/APB_WDT32.v
../verilog/rtl/AHB_sys_0/APB_sys_0/APB_TIMER32.v
../verilog/rtl/AHB_sys_0/APB_sys_0/APB_PWM32.v
../verilog/rtl/AHB_sys_0/APB_sys_0/AHB_2_APB.v
../verilog/rtl/AHB_sys_0/APB_sys_0/APB_bus0.v
../verilog/rtl/AHB_sys_0/APB_sys_0/APB_sys_0.v

#-y ../verilog/rtl/IPs
../verilog/rtl/IPs/TIMER32.v
../verilog/rtl/IPs/PWM32.v
../verilog/rtl/IPs/WDT32.v
../verilog/rtl/IPs/spi_master.v
../verilog/rtl/IPs/i2c_master.v
../verilog/rtl/IPs/GPIO.v
../verilog/rtl/IPs/APB_UART.v
../verilog/rtl/IPs/APB_SPI.v
../verilog/rtl/IPs/APB_I2C.v
../verilog/rtl/IPs/DMC_32x16HC.v
../verilog/rtl/IPs/QSPI_XIP_CTRL.v
../verilog/rtl/IPs/AHBSRAM.v
../verilog/rtl/IPs/DFFRAM.v
../verilog/rtl/IPs/DFFRAMBB.v
#../verilog/rtl/IPs/RAM_4Kx32.v
../verilog/rtl/IPs/RAM_3Kx32.v
../verilog/rtl/acc/AHB_SPM.v

../verilog/rtl/soc_core.v
../verilog/rtl/NfiVe32.v 
../verilog/rtl/DFFRFile.v 

N5_SoC_TB.v
sst26wf080b.v
23LC512.v