)]}'
{
  "commit": "336e082659fb914bf7224732383dff5c0dae0178",
  "tree": "dae97d1a06287d1301ba5e609c15dfa780d5fc2a",
  "parents": [
    "08cd6eba30b5b59bbd33a808a9173203d7a7175b"
  ],
  "author": {
    "name": "Matt Venn",
    "email": "matt@mattvenn.net",
    "time": "Mon Nov 16 12:03:29 2020 +0100"
  },
  "committer": {
    "name": "Matt Venn",
    "email": "matt@mattvenn.net",
    "time": "Mon Nov 16 12:03:29 2020 +0100"
  },
  "message": "add missing signals\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "acfd8ad5320df66d1b615b9b67308e9d45160561",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/uart_wb/uart_wb_tb.v",
      "new_id": "56b93f6303772de41f50643c08afd30c4a99a3ec",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/uart_wb/uart_wb_tb.v"
    },
    {
      "type": "modify",
      "old_id": "62a3ea60c1db6bfa20f220b90dc85d906c4bdd94",
      "old_mode": 33188,
      "old_path": "verilog/rtl/simpleuart.v",
      "new_id": "66e19159db58874e6a215a484c4b24adb8730dd5",
      "new_mode": 33188,
      "new_path": "verilog/rtl/simpleuart.v"
    }
  ]
}