diff --git a/verilog/dv/harness/mgmt_soc/defs.h b/verilog/dv/harness/defs.h
similarity index 66%
rename from verilog/dv/harness/mgmt_soc/defs.h
rename to verilog/dv/harness/defs.h
index e2d777f..d9eec3a 100644
--- a/verilog/dv/harness/mgmt_soc/defs.h
+++ b/verilog/dv/harness/defs.h
@@ -12,15 +12,17 @@
 extern uint32_t flashio_worker_begin;
 extern uint32_t flashio_worker_end;
 
-// IOs: UART (0x2000_0000), GPIO (0x2100_0000), LA (0x2200_0000)
+// UART (0x2000_0000)
 #define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
 #define reg_uart_data   (*(volatile uint32_t*)0x20000004)
 
+// GPIO (0x2100_0000)
 #define reg_gpio_data (*(volatile uint32_t*)0x21000000)
 #define reg_gpio_ena  (*(volatile uint32_t*)0x21000004)
 #define reg_gpio_pu   (*(volatile uint32_t*)0x21000008)
 #define reg_gpio_pd   (*(volatile uint32_t*)0x2100000c)
 
+// Logic Analyzer (0x2200_0000)
 #define reg_la0_data (*(volatile uint32_t*)0x22000000)
 #define reg_la1_data (*(volatile uint32_t*)0x22000004)
 #define reg_la2_data (*(volatile uint32_t*)0x22000008)
@@ -31,6 +33,49 @@
 #define reg_la2_ena (*(volatile uint32_t*)0x22000018)
 #define reg_la3_ena (*(volatile uint32_t*)0x2200001c)
 
+// Mega Project Control (0x2300_0000)
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x23000000)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x23000004)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x23000008)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x2300000c)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x23000010)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x23000014)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x23000018)
+
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x2300001c)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x23000020)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x23000024)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x23000028)
+
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x2300002c)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x23000030)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x23000034)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x23000038)
+
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x2300003c)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x23000040)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x23000044)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x23000048)
+
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x2300004c)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x23000050)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x23000054)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x23000058)
+
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x2300005c)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x23000060)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x23000064)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x23000068)
+
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x2300006c)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x23000070)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x23000074)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x23000078)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x2300007c)
+
+// Mega Project Slaves (0x3000_0000)
+#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+
 // Flash Control SPI Configuration (2D00_0000)
 #define reg_spictrl (*(volatile uint32_t*)0x2D000000)         
 
diff --git a/verilog/dv/harness/mgmt_soc/Makefile b/verilog/dv/harness/mgmt_soc/Makefile
index c934af3..9f185c0 100644
--- a/verilog/dv/harness/mgmt_soc/Makefile
+++ b/verilog/dv/harness/mgmt_soc/Makefile
@@ -3,7 +3,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = gpio mem uart perf hkspi sysctrl xbar
+PATTERNS = gpio mem uart perf hkspi sysctrl mprj_ctrl
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \
diff --git a/verilog/dv/harness/mgmt_soc/gpio/Makefile b/verilog/dv/harness/mgmt_soc/gpio/Makefile
index e9253c0..719e42b 100644
--- a/verilog/dv/harness/mgmt_soc/gpio/Makefile
+++ b/verilog/dv/harness/mgmt_soc/gpio/Makefile
@@ -1,3 +1,8 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
 .SUFFIXES:
 
 PATTERN = gpio
@@ -7,14 +12,14 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
 	$< -o $@
 
 %.vcd: %.vvp
 	vvp $<
 
-%.elf: %.c ../sections.lds ../start.s
-	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
 
 %.hex: %.elf
 	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
diff --git a/verilog/dv/harness/mgmt_soc/gpio/gpio.c b/verilog/dv/harness/mgmt_soc/gpio/gpio.c
index 17a4885..0d9caf5 100644
--- a/verilog/dv/harness/mgmt_soc/gpio/gpio.c
+++ b/verilog/dv/harness/mgmt_soc/gpio/gpio.c
@@ -1,4 +1,4 @@
-#include "../defs.h"
+#include "../../defs.h"
 
 // --------------------------------------------------------
 
diff --git a/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v
index c20ba26..35c8cf3 100644
--- a/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v
@@ -20,7 +20,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness.v"
+`include "harness_chip.v"
 `include "spiflash.v"
 
 module gpio_tb;
@@ -151,7 +151,7 @@
 	assign VSS = 1'b0;
 	assign VDD1V8 = 1'b1;
 
-	harness uut (
+	harness_chip uut (
 		.vdd	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/Makefile b/verilog/dv/harness/mgmt_soc/hkspi/Makefile
index 2850baa..07ea208 100644
--- a/verilog/dv/harness/mgmt_soc/hkspi/Makefile
+++ b/verilog/dv/harness/mgmt_soc/hkspi/Makefile
@@ -1,3 +1,8 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
 .SUFFIXES:
 
 PATTERN = hkspi
@@ -7,14 +12,14 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
 	$< -o $@
-
+	
 %.vcd: %.vvp
 	vvp $<
 
-%.elf: %.c ../sections.lds ../start.s
-	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
 
 %.hex: %.elf
 	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< /dev/stdout | sed -e '1 s/@10000000/@00000000/; 2,65537 d;' > $@
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c b/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c
index d572727..a415214 100644
--- a/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c
+++ b/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c
@@ -1,4 +1,4 @@
-#include "../defs.h"
+#include "../../defs.h"
 
 // --------------------------------------------------------
 
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v
index 0edc43d..09d1dab 100644
--- a/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v
@@ -4,7 +4,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness.v"
+`include "harness_chip.v"
 `include "spiflash.v"
 `include "tbuart.v"
 
@@ -167,31 +167,31 @@
 		write_byte(8'h00);	// Address (register 3 = product ID)
 	    read_byte(tbdata);
 	    $display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
 	    read_byte(tbdata);
 	    $display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
-		if(tbdata != 8'h14) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h14) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
 	    read_byte(tbdata);
 	    $display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
-		if(tbdata != 8'h56) begin $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; end
+		if(tbdata !== 8'h56) begin $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; end
 	    read_byte(tbdata);
 	    $display("Read register 3 = 0x%02x (should be 0x05)", tbdata);
-		if(tbdata != 8'h05) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h05) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
 	    read_byte(tbdata);
 	    $display("Read register 4 = 0x%02x (should be 0x07)", tbdata);
-		if(tbdata != 8'h07) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h07) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
 	    read_byte(tbdata);
 	    $display("Read register 5 = 0x%02x (should be 0x01)", tbdata);
-		if(tbdata != 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
 	    read_byte(tbdata);
 	    $display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
 	    read_byte(tbdata);
 	    $display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
 	    read_byte(tbdata);
 	    $display("Read register 8 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
 		
         end_csb();
 
@@ -209,7 +209,7 @@
 	assign VSS = 1'b0;
 	assign VDD1V8 = 1'b1;
 
-	harness uut (
+	harness_chip uut (
 		.vdd	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/mem/Makefile b/verilog/dv/harness/mgmt_soc/mem/Makefile
index d63df1b..fc85291 100644
--- a/verilog/dv/harness/mgmt_soc/mem/Makefile
+++ b/verilog/dv/harness/mgmt_soc/mem/Makefile
@@ -1,4 +1,9 @@
 
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
 .SUFFIXES:
 
 PATTERN = mem
@@ -8,14 +13,14 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
 	$< -o $@
 
 %.vcd: %.vvp
 	vvp $<
 
-%.elf: %.c ../sections.lds ../start.s
-	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
 
 %.hex: %.elf
 	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
diff --git a/verilog/dv/harness/mgmt_soc/mem/mem.c b/verilog/dv/harness/mgmt_soc/mem/mem.c
index 0bff65d..31d0f75 100644
--- a/verilog/dv/harness/mgmt_soc/mem/mem.c
+++ b/verilog/dv/harness/mgmt_soc/mem/mem.c
@@ -1,4 +1,4 @@
-#include "../defs.h"
+#include "../../defs.h"
 
 // --------------------------------------------------------
 
diff --git a/verilog/dv/harness/mgmt_soc/mem/mem_tb.v b/verilog/dv/harness/mgmt_soc/mem/mem_tb.v
index 09bb0a7..0d0c93d 100644
--- a/verilog/dv/harness/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/harness/mgmt_soc/mem/mem_tb.v
@@ -20,7 +20,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness.v"
+`include "harness_chip.v"
 `include "spiflash.v"
 
 module mem_tb;
@@ -146,7 +146,7 @@
 	assign VDD3V3 = 1'b1;
 	assign VDD1V8 = 1'b1;
 
-	harness uut (
+	harness_chip uut (
 		.vdd	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile
new file mode 100644
index 0000000..3b396d7
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile
@@ -0,0 +1,37 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
+.SUFFIXES:
+
+PATTERN = mprj_ctrl
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c  $(FIRMWARE_PATH)/sections.lds  $(FIRMWARE_PATH)/start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,  $(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@  $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
\ No newline at end of file
diff --git a/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c
new file mode 100644
index 0000000..97b8148
--- /dev/null
+++ b/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c
@@ -0,0 +1,38 @@
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+	Mega-Project IO Control Test
+*/
+
+void main()
+{
+    /* All GPIO pins are configured to be output */
+	reg_gpio_data = 0;
+	reg_gpio_ena =  0x0000;
+
+	// start test
+	reg_gpio_data = 0xA040;
+
+    // Write to IO Control
+    reg_mprj_io_0 = 0x004F;
+    if(0x004F != reg_mprj_io_0) reg_gpio_data = 0xAB40;
+	reg_gpio_data = 0xAB41;
+
+    // Write to IO Control 
+    reg_mprj_io_1 = 0x005F;
+    if(0x005F != reg_mprj_io_1) reg_gpio_data = 0xAB50;
+	reg_gpio_data = 0xAB51;
+
+    // Write to IO Control
+    reg_mprj_io_2 = 0x006F;
+    if(0x006F != reg_mprj_io_2) reg_gpio_data = 0xAB60;
+	reg_gpio_data = 0xAB61;
+
+    // Write to IO Control
+    reg_mprj_io_3 = 0xF0F5;
+    if(0xF0F5 != reg_mprj_io_3) reg_gpio_data = 0xAB70;
+	reg_gpio_data = 0xAB71;
+}
+
diff --git a/verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v b/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
similarity index 60%
rename from verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v
rename to verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index b9357f0..bcbbe12 100644
--- a/verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v
+++ b/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -1,10 +1,10 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness.v"
+`include "harness_chip.v"
 `include "spiflash.v"
 
-module xbar_tb;
+module mprj_ctrl_tb;
 	reg XCLK;
 	reg XI;
 
@@ -22,6 +22,10 @@
 	wire flash_io3;
 	wire SDO;
 
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
 	always #10 XCLK <= (XCLK === 1'b0);
 	always #220 XI <= (XI === 1'b0);
 
@@ -31,57 +35,41 @@
 	end
 
 	initial begin
-		$dumpfile("xbar_tb.vcd");
-		$dumpvars(0, xbar_tb);
+		$dumpfile("mprj_ctrl_tb.vcd");
+		$dumpvars(0, mprj_ctrl_tb);
 		repeat (25) begin
 			repeat (1000) @(posedge XCLK);
 			$display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test Crossbar Switch (RTL) Failed");
-		 $display("%c[0m", 27);
+		$display ("Monitor: Timeout, Test Mega-Project (RTL) Failed");
+		 $display("%c[0m",27);
 		$finish;
 	end
 
 	always @(gpio) begin
 		if(gpio == 16'hA040) begin
-			$display("Crossbar Switch Test started");
+			$display("Mega-Project control Test started");
 		end
 		else if(gpio == 16'hAB40) begin
 			$display("%c[1;31m",27);
-			$display("Monitor: Crossbar test R/W from QSPI CTRL slave failed.");
+			$display("Monitor: IO control R/W failed");
 			$display("%c[0m",27);
 			$finish;
 		end
 		else if(gpio == 16'hAB41) begin
-			$display("Monitor: Crossbar test R/W from QSPI CTRL slave passed");
+			$display("Monitor: IO control R/W passed");
 		end
         else if(gpio == 16'hAB50) begin
             $display("%c[1;31m",27);
-			$display("Monitor: Crossbar test R/W from storage area failed.");
+			$display("Monitor: power control R/W failed");
 			$display("%c[0m",27);
 			$finish;
         end else if(gpio == 16'hAB51) begin
-			$display("Monitor: Crossbar test R/W from storage area passed.");
-        end
-        else if(gpio == 16'hAB60) begin
-            $display("%c[1;31m",27);
-			$display("Monitor: Crossbar test R/W from mega project 1st slave failed.");
-			$display("%c[0m",27);
-			$finish;
-        end else if(gpio == 16'hAB61) begin
-			$display("Monitor: Crossbar test R/W from mega project 1st slave passed.");
-        end
-        else if(gpio == 16'hAB70) begin
-            $display("%c[1;31m",27);
-			$display("Monitor: Crossbar test R/W from mega project 2nd slave passed.");
-			$display("%c[0m",27);
-			$finish;
-        end else if(gpio == 16'hAB71) begin
-			$display("Monitor: Crossbar test R/W from mega project 2nd slave passed.");
-		    $display("Monitor: Timeout, Test Crossbar Switch (RTL) Passed.");
+			$display("Monitor: power control R/W passed");
+            $display("Monitor: Mega-Project control (RTL) test passed.");
             $finish;
-        end
+        end			
 	end
 
 	initial begin
@@ -107,11 +95,11 @@
 	assign VDD1V8 = 1'b1;
 	assign VDD3V3 = 1'b1;
 
-	harness uut (
+	harness_chip uut (
 		.vdd	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
-		.xi	  (XI),
+		.xi	      (XI),
 		.xclk	  (XCLK),
 		.SDI	  (SDI),
 		.SDO	  (SDO),
@@ -137,7 +125,7 @@
 	);
 
 	spiflash #(
-		.FILENAME("xbar.hex")
+		.FILENAME("mprj_ctrl.hex")
 	) spiflash (
 		.csb(flash_csb),
 		.clk(flash_clk),
diff --git a/verilog/dv/harness/mgmt_soc/perf/Makefile b/verilog/dv/harness/mgmt_soc/perf/Makefile
index dad371f..b24bd84 100644
--- a/verilog/dv/harness/mgmt_soc/perf/Makefile
+++ b/verilog/dv/harness/mgmt_soc/perf/Makefile
@@ -1,3 +1,8 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
 .SUFFIXES:
 
 PATTERN = perf
@@ -7,14 +12,14 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
 	$< -o $@
 	
 %.vcd: %.vvp
 	vvp $<
 
-%.elf: %.c ../sections.lds ../start.s
-	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
 
 %.hex: %.elf
 	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
diff --git a/verilog/dv/harness/mgmt_soc/perf/perf.c b/verilog/dv/harness/mgmt_soc/perf/perf.c
index 4dc34b1..bd94f5d 100644
--- a/verilog/dv/harness/mgmt_soc/perf/perf.c
+++ b/verilog/dv/harness/mgmt_soc/perf/perf.c
@@ -1,4 +1,4 @@
-#include "../defs.h"
+#include "../../defs.h"
 
 // --------------------------------------------------------
 
diff --git a/verilog/dv/harness/mgmt_soc/perf/perf_tb.v b/verilog/dv/harness/mgmt_soc/perf/perf_tb.v
index edd10ba..3e5edbc 100644
--- a/verilog/dv/harness/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/harness/mgmt_soc/perf/perf_tb.v
@@ -20,7 +20,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness.v"
+`include "harness_chip.v"
 `include "spiflash.v"
 
 module striVe_perf_tb;
@@ -122,7 +122,7 @@
 	assign VDD1V8 = 1'b1;
 	assign VDD3V3 = 1'b1;
 
-	harness uut (
+	harness_chip uut (
 		.vdd	  (VDD3V3  ),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/Makefile b/verilog/dv/harness/mgmt_soc/sysctrl/Makefile
index 0b43365..a4a14a6 100644
--- a/verilog/dv/harness/mgmt_soc/sysctrl/Makefile
+++ b/verilog/dv/harness/mgmt_soc/sysctrl/Makefile
@@ -1,3 +1,8 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
 .SUFFIXES:
 
 PATTERN = sysctrl
@@ -7,14 +12,14 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
 	$< -o $@
 
 %.vcd: %.vvp
 	vvp $<
 
-%.elf: %.c ../sections.lds ../start.s
-	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
 
 %.hex: %.elf
 	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c
index a4a6762..023a08c 100644
--- a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c
+++ b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c
@@ -1,4 +1,4 @@
-#include "../defs.h"
+#include "../../defs.h"
 
 // --------------------------------------------------------
 
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v
index d1e4439..4932e0d 100644
--- a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -1,7 +1,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness.v"
+`include "harness_chip.v"
 `include "spiflash.v"
 
 module sysctrl_tb;
@@ -127,7 +127,7 @@
 	assign VDD1V8 = 1'b1;
 	assign VDD3V3 = 1'b1;
 
-	harness uut (
+	harness_chip uut (
 		.vdd	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/uart/Makefile b/verilog/dv/harness/mgmt_soc/uart/Makefile
index 057be64..3ce3936 100644
--- a/verilog/dv/harness/mgmt_soc/uart/Makefile
+++ b/verilog/dv/harness/mgmt_soc/uart/Makefile
@@ -1,4 +1,8 @@
 # ---- Test patterns for project striVe ----
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
 
 .SUFFIXES:
 
@@ -9,14 +13,14 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
+	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
 	$< -o $@
 
 %.vcd: %.vvp
 	vvp $<
 
-%.elf: %.c ../sections.lds ../start.s
-	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
 
 %.hex: %.elf
 	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
diff --git a/verilog/dv/harness/mgmt_soc/uart/uart.c b/verilog/dv/harness/mgmt_soc/uart/uart.c
index fe362f8..bf21144 100644
--- a/verilog/dv/harness/mgmt_soc/uart/uart.c
+++ b/verilog/dv/harness/mgmt_soc/uart/uart.c
@@ -1,19 +1,5 @@
-#include "../defs.h"
-
-// --------------------------------------------------------
-
-void putchar(char c)
-{
-	if (c == '\n')
-		putchar('\r');
-	reg_uart_data = c;
-}
-
-void print(const char *p)
-{
-	while (*p)
-		putchar(*(p++));
-}
+#include "../../defs.h"
+#include "../stub.c"
 
 // --------------------------------------------------------
 
diff --git a/verilog/dv/harness/mgmt_soc/uart/uart_tb.v b/verilog/dv/harness/mgmt_soc/uart/uart_tb.v
index 56c76f2..c031659 100644
--- a/verilog/dv/harness/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/harness/mgmt_soc/uart/uart_tb.v
@@ -20,7 +20,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness.v"
+`include "harness_chip.v"
 `include "spiflash.v"
 `include "tbuart.v"
 
@@ -105,7 +105,7 @@
 	assign VDD1V8 = 1'b1;
 	assign VDD3V3 = 1'b1;
 
-	harness uut (
+	harness_chip uut (
 		.vdd	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/xbar/Makefile b/verilog/dv/harness/mgmt_soc/xbar/Makefile
deleted file mode 100644
index 5302d06..0000000
--- a/verilog/dv/harness/mgmt_soc/xbar/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-.SUFFIXES:
-
-PATTERN = xbar
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -I ../ -I ../../../../ip -I ../../../../rtl \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c ../sections.lds ../start.s
-	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $<
-
-%.hex: %.elf
-	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/harness/mgmt_soc/xbar/xbar.c b/verilog/dv/harness/mgmt_soc/xbar/xbar.c
deleted file mode 100644
index 5565f1f..0000000
--- a/verilog/dv/harness/mgmt_soc/xbar/xbar.c
+++ /dev/null
@@ -1,41 +0,0 @@
-#include "../defs.h"
-
-// --------------------------------------------------------
-
-/*
-	Crosbbar Switch Test
-        - Reads default value of SPI-Controlled registers
-        - Flags failure/success using gpio
-*/
-void main()
-{
-	int i;
-
-    reg_gpio_data = 0;
-	reg_gpio_ena =  0x0000;
-
-	// start test
-	reg_gpio_data = 0xA040;
-
-    // Write & Read from QSPI CTRL Slave
-    qspi_ctrl_slave = 0xA0A1; 
-    if(0xA0A1 != qspi_ctrl_slave) reg_gpio_data = 0xAB40;
-	reg_gpio_data = 0xAB41;
-
-    // Write & Read from storage area Slave
-    storage_area_slave = 0xB0B1; 
-    if(0xB0B1 != storage_area_slave) reg_gpio_data = 0xAB50;
-	reg_gpio_data = 0xAB51;
-
-    // Write & Read from Mega Project 1st slave
-    mega_any_slave1 = 0xC0C1; 
-    if(0xC0C1 != mega_any_slave1) reg_gpio_data = 0xAB60;
-	reg_gpio_data = 0xAB61;
-
-    // Write & Read from Mega Project 1st slave
-    mega_any_slave2 = 0xD0D1; 
-    if(0xD0D1 != mega_any_slave2) reg_gpio_data = 0xAB70;
-	reg_gpio_data = 0xAB71;
-
-}
-
diff --git a/verilog/dv/harness/mprj_counter/Makefile b/verilog/dv/harness/mprj_counter/Makefile
new file mode 100644
index 0000000..6b5248c
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/Makefile
@@ -0,0 +1,18 @@
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = io_ports la_test1 la_test2
+
+all:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+	done
+
+clean:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make clean ) ; \
+	done
+
+.PHONY: clean all
diff --git a/verilog/dv/harness/mprj_counter/README.md b/verilog/dv/harness/mprj_counter/README.md
new file mode 100644
index 0000000..16afd68
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/README.md
@@ -0,0 +1,20 @@
+# Mega-Project Counter Tests
+
+The directory includes three tests for the counter mega-project example: 
+
+1) IO Ports Test: 
+
+	* Configures the Mega-project lower 8 IO pins as outputs
+	* Observes the counter value through the configured pins in the testbench
+
+ 2) Logic Analyzer Test 1:
+ 
+	* Configures LA probes [31:0] as inputs to the management SoC to monitor the counter value 
+	* Configures LA probes [63:32] as outputs from the management SoC to set the counter initial value 
+	* Flags when counter value exceeds 500 through the management SoC gpio
+	* Outputs message to the UART when the test concludes successfuly
+  
+ 3) Logic Analyzer Test 2:
+ 
+	* Configures LA probes [64] and [65] as outputs from the management SoC to set counter clock and reset values
+	* Provides counter clock and monitors the counter value after five clock cycles
diff --git a/verilog/dv/harness/mprj_counter/io_ports/Makefile b/verilog/dv/harness/mprj_counter/io_ports/Makefile
new file mode 100644
index 0000000..8f0cd33
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/io_ports/Makefile
@@ -0,0 +1,37 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
+.SUFFIXES:
+
+PATTERN = io_ports
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
\ No newline at end of file
diff --git a/verilog/dv/harness/mprj_counter/io_ports/io_ports.c b/verilog/dv/harness/mprj_counter/io_ports/io_ports.c
new file mode 100644
index 0000000..e4b9cf4
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/io_ports/io_ports.c
@@ -0,0 +1,40 @@
+#include "../../defs.h"
+
+/*
+	IO Test:
+		- Configures MPRJ lower 8-IO pins as outputs
+		- Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
+*/
+
+void main()
+{
+	/* 
+	IO Control Registers
+	
+	| DM     | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | ENH   | HLDH_N | OEB_N |
+	| 3-bits | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit  | 1-bit |
+
+	Output: 0000_0110_0000_1110  (0x060E)
+	| DM  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | ENH | HLDH_N | OEB_N |
+	| 110 | 0      | 0      | 0     | 0       | 1       | 1   | 1      | 0     |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x010F)
+	| DM  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | ENH | HLDH_N | OEB_N |
+	| 001 | 0      | 0      | 0     | 0       | 1       |  1  | 1      | 1     |
+
+	*/
+
+	// Configure lower 8-IOs as output
+	// Observe counter value in the testbench
+	reg_mprj_io_0 =  0x060E;
+	reg_mprj_io_1 =  0x060E;
+	reg_mprj_io_2 =  0x060E;
+	reg_mprj_io_3 =  0x060E;
+	reg_mprj_io_4 =  0x060E;
+	reg_mprj_io_5 =  0x060E;
+	reg_mprj_io_6 =  0x060E;
+	reg_mprj_io_7 =  0x060E;
+
+}
+
diff --git a/verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v b/verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v
new file mode 100644
index 0000000..e30f139
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v
@@ -0,0 +1,139 @@
+
+`timescale 1 ns / 1 ps
+
+`include "harness_chip.v"
+`include "spiflash.v"
+
+module io_ports_tb;
+	reg XCLK;
+	reg XI;
+
+	reg real adc_h, adc_l;
+	reg real adc_0, adc_1;
+	reg real comp_n, comp_p;
+    reg SDI, CSB, SCK, RSTB;
+	wire SDO;
+
+    wire [15:0] gpio;
+    wire [31:0] mprj_io;
+	wire [7:0] mprj_io_0;
+
+	assign mprj_io_0 = mprj_io[7:0];
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 XCLK <= (XCLK === 1'b0);
+	always #220 XI <= (XI === 1'b0);
+
+	initial begin
+		XI = 0;
+		XCLK = 0;
+	end
+
+	initial begin
+		$dumpfile("io_ports.vcd");
+		$dumpvars(0, io_ports_tb);
+
+		// Repeat cycles of 1000 XCLK edges as needed to complete testbench
+		repeat (25) begin
+			repeat (1000) @(posedge XCLK);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		// Observe Output pins [7:0]
+		wait(mprj_io_0==8'h01);
+		wait(mprj_io_0==8'h02);
+		wait(mprj_io_0==8'h03);
+    	wait(mprj_io_0==8'h04);
+		wait(mprj_io_0==8'h05);
+        wait(mprj_io_0==8'h06);
+		wait(mprj_io_0==8'h07);
+        wait(mprj_io_0==8'h08);
+		wait(mprj_io_0==8'h09);
+        wait(mprj_io_0==8'h0A);   
+		wait(mprj_io_0==8'hFF);
+		wait(mprj_io_0==8'h00);
+		$display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+		$finish;
+	end
+
+	initial begin
+		CSB <= 1'b1;
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+		CSB <= 1'b0;	    // Apply CSB to start transmission
+	end
+
+	always @(mprj_io) begin
+		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+	end
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+
+	assign VSS = 1'b0;
+	assign VDD1V8 = 1'b1;
+	assign VDD3V3 = 1'b1;
+
+	harness_chip uut (
+		.vdd	  (VDD3V3),
+		.vdd1v8	  (VDD1V8),
+		.vss	  (VSS),
+		.xi	  	  (XI),
+		.xclk	  (XCLK),
+		.SDI	  (SDI),
+		.SDO	  (SDO),
+		.CSB	  (CSB),
+		.SCK	  (SCK),
+		.ser_rx	  (1'b0),
+		.ser_tx	  (tbuart_rx),
+		.irq	  (1'b0),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.flash_io2(flash_io2),
+		.flash_io3(flash_io3),
+		.adc_high (adc_h),
+		.adc_low  (adc_l),
+		.adc0_in  (adc_0),
+		.adc1_in  (adc_1),
+		.RSTB	  (RSTB),
+		.comp_inp (comp_p),
+		.comp_inn (comp_n)
+	);
+
+	spiflash #(
+		.FILENAME("io_ports.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(flash_io2),
+		.io3(flash_io3)
+	);
+
+endmodule
diff --git a/verilog/dv/harness/mprj_counter/la_test1/Makefile b/verilog/dv/harness/mprj_counter/la_test1/Makefile
new file mode 100644
index 0000000..da557a6
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/la_test1/Makefile
@@ -0,0 +1,37 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
+.SUFFIXES:
+
+PATTERN = la_test1
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
\ No newline at end of file
diff --git a/verilog/dv/harness/mprj_counter/la_test1/la_test1.c b/verilog/dv/harness/mprj_counter/la_test1/la_test1.c
new file mode 100644
index 0000000..1404a1e
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/la_test1/la_test1.c
@@ -0,0 +1,51 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+// --------------------------------------------------------
+
+/*
+	MPRJ Logic Analyzer Test:
+		- Observes counter value through LA probes [31:0] 
+		- Sets counter initial value through LA probes [63:32]
+		- Flags when counter value exceeds 500 through the management SoC gpio
+		- Outputs message to the UART when the test concludes successfuly
+*/
+
+void main()
+{
+
+	// All GPIO pins are configured to be output
+	// Used to flad the start/end of a test 
+	reg_gpio_data = 0;
+	reg_gpio_ena =  0x0000;
+
+	// Set UART clock to 64 kbaud
+	reg_uart_clkdiv = 625;
+
+	// Configure LA probes [31:0], [127:64] as inputs to the cpu 
+	// Configure LA probes [63:32] as outputs from the cpu
+	reg_la0_ena = 0xFFFFFFFF;    // [31:0]
+	reg_la1_ena = 0x00000000;    // [63:32]
+	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
+	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
+
+	// Flag start of the test 
+	reg_gpio_data = 0xAB40;
+
+	// Set Counter value to zero through LA probes [63:32]
+	reg_la1_data = 0x00000000;
+
+	// Configure LA probes from [63:32] as inputs to disable counter write
+	reg_la1_ena  = 0xFFFFFFFF;    
+
+	while (1) {
+		if (reg_la0_data > 0x1F4) {
+			reg_gpio_data = 0xAB41;
+			break;
+		}
+	}
+	print("\n");
+	print("Monitor: Test 2 Passed\n\n");
+	reg_gpio_data = 0xAB51;
+}
+
diff --git a/verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v b/verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v
new file mode 100644
index 0000000..1eb6885
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v
@@ -0,0 +1,132 @@
+
+`timescale 1 ns / 1 ps
+
+`include "harness_chip.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module la_test1_tb;
+	reg XCLK;
+	reg XI;
+
+	reg real adc_h, adc_l;
+	reg real adc_0, adc_1;
+	reg real comp_n, comp_p;
+    reg SDI, CSB, SCK, RSTB;
+	wire SDO;
+
+    wire [15:0] gpio;
+    wire [31:0] mprj_io;
+	wire [7:0] mprj_io_0;
+
+	assign mprj_io_0 = mprj_io[7:0];
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 XCLK <= (XCLK === 1'b0);
+	always #220 XI <= (XI === 1'b0);
+
+	initial begin
+		XI = 0;
+		XCLK = 0;
+	end
+
+	initial begin
+		$dumpfile("la_test1.vcd");
+		$dumpvars(0, la_test1_tb);
+
+		// Repeat cycles of 1000 XCLK edges as needed to complete testbench
+		repeat (200) begin
+			repeat (1000) @(posedge XCLK);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		wait(gpio == 16'hAB40);
+		$display("LA Test 1 started");
+		wait(gpio == 16'hAB41);
+		wait(gpio == 16'hAB51);
+		#10000;
+		$finish;
+	end
+
+	initial begin
+		CSB <= 1'b1;
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+		CSB <= 1'b0;	    // Apply CSB to start transmission
+	end
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+
+	assign VSS = 1'b0;
+	assign VDD1V8 = 1'b1;
+	assign VDD3V3 = 1'b1;
+
+	harness_chip uut (
+		.vdd	  (VDD3V3),
+		.vdd1v8	  (VDD1V8),
+		.vss	  (VSS),
+		.xi	  	  (XI),
+		.xclk	  (XCLK),
+		.SDI	  (SDI),
+		.SDO	  (SDO),
+		.CSB	  (CSB),
+		.SCK	  (SCK),
+		.ser_rx	  (1'b0),
+		.ser_tx	  (tbuart_rx),
+		.irq	  (1'b0),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.flash_io2(flash_io2),
+		.flash_io3(flash_io3),
+		.adc_high (adc_h),
+		.adc_low  (adc_l),
+		.adc0_in  (adc_0),
+		.adc1_in  (adc_1),
+		.RSTB	  (RSTB),
+		.comp_inp (comp_p),
+		.comp_inn (comp_n)
+	);
+
+	spiflash #(
+		.FILENAME("la_test1.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(flash_io2),
+		.io3(flash_io3)
+	);
+
+	// Testbench UART
+	tbuart tbuart (
+		.ser_rx(tbuart_rx)
+	);
+
+endmodule
diff --git a/verilog/dv/harness/mprj_counter/la_test2/Makefile b/verilog/dv/harness/mprj_counter/la_test2/Makefile
new file mode 100644
index 0000000..c8b727b
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/la_test2/Makefile
@@ -0,0 +1,37 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
+.SUFFIXES:
+
+PATTERN = la_test2
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
\ No newline at end of file
diff --git a/verilog/dv/harness/mprj_counter/la_test2/la_test2.c b/verilog/dv/harness/mprj_counter/la_test2/la_test2.c
new file mode 100644
index 0000000..e9f5ece
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/la_test2/la_test2.c
@@ -0,0 +1,47 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+/*
+	MPRJ LA Test:
+		- Sets counter clk through LA[64]
+		- Sets counter rst through LA[65] 
+		- Observes count value for five clk cycle through LA[31:0]
+*/
+
+int clk = 0;
+int i;
+
+void main()
+{
+	// All GPIO pins are configured to be output
+	// Used to flad the start/end of a test 
+	reg_gpio_data = 0;
+	reg_gpio_ena =  0x0000;
+
+	// Configure All LA probes as inputs to the cpu 
+	reg_la0_ena = 0xFFFFFFFF;    // [31:0]
+	reg_la1_ena = 0xFFFFFFFF;    // [63:32]
+	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
+	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
+
+	// Flag start of the test
+	reg_gpio_data = 0xAB60;
+
+	// Configure LA[64] LA[65] as outputs from the cpu
+	reg_la2_ena  = 0xFFFFFFFC; 
+
+	// Set clk & reset to one
+	reg_la2_data = 0x00000003;
+
+	// Toggle clk & de-assert reset
+	for (i=0; i<11; i=i+1) {
+		clk = !clk;
+		reg_la2_data = 0x00000000 | clk;
+	}
+
+	if (reg_la0_data == 0x05) {
+		reg_gpio_data = 0xAB61;
+	}
+
+}
+
diff --git a/verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v b/verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v
new file mode 100644
index 0000000..a3e6223
--- /dev/null
+++ b/verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v
@@ -0,0 +1,125 @@
+
+`timescale 1 ns / 1 ps
+
+`include "harness_chip.v"
+`include "spiflash.v"
+
+module la_test2_tb;
+	reg XCLK;
+	reg XI;
+
+	reg real adc_h, adc_l;
+	reg real adc_0, adc_1;
+	reg real comp_n, comp_p;
+    reg SDI, CSB, SCK, RSTB;
+	wire SDO;
+
+    wire [15:0] gpio;
+    wire [31:0] mprj_io;
+	wire [7:0] mprj_io_0;
+
+	assign mprj_io_0 = mprj_io[7:0];
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 XCLK <= (XCLK === 1'b0);
+	always #220 XI <= (XI === 1'b0);
+
+	initial begin
+		XI = 0;
+		XCLK = 0;
+	end
+
+	initial begin
+		$dumpfile("la_test2.vcd");
+		$dumpvars(0, la_test2_tb);
+
+		// Repeat cycles of 1000 XCLK edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge XCLK);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		wait(gpio == 16'h AB60);
+		$display("Monitor: Test 2 MPRJ-Logic Analyzer Started");
+		wait(gpio == 16'h AB61);
+		$display("Monitor: Test 2 MPRJ-Logic Analyzer Passed");
+		$finish;
+	end
+
+	initial begin
+		CSB <= 1'b1;
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+		CSB <= 1'b0;	    // Apply CSB to start transmission
+	end
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+
+	assign VSS = 1'b0;
+	assign VDD1V8 = 1'b1;
+	assign VDD3V3 = 1'b1;
+
+	harness_chip uut (
+		.vdd	  (VDD3V3),
+		.vdd1v8	  (VDD1V8),
+		.vss	  (VSS),
+		.xi	  	  (XI),
+		.xclk	  (XCLK),
+		.SDI	  (SDI),
+		.SDO	  (SDO),
+		.CSB	  (CSB),
+		.SCK	  (SCK),
+		.ser_rx	  (1'b0),
+		.ser_tx	  (),
+		.irq	  (1'b0),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.flash_io2(flash_io2),
+		.flash_io3(flash_io3),
+		.adc_high (adc_h),
+		.adc_low  (adc_l),
+		.adc0_in  (adc_0),
+		.adc1_in  (adc_1),
+		.RSTB	  (RSTB),
+		.comp_inp (comp_p),
+		.comp_inn (comp_n)
+	);
+
+	spiflash #(
+		.FILENAME("la_test2.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(flash_io2),
+		.io3(flash_io3)
+	);
+
+endmodule
diff --git a/verilog/dv/harness/mgmt_soc/sections.lds b/verilog/dv/harness/sections.lds
similarity index 93%
rename from verilog/dv/harness/mgmt_soc/sections.lds
rename to verilog/dv/harness/sections.lds
index 4392c6d..8482887 100644
--- a/verilog/dv/harness/mgmt_soc/sections.lds
+++ b/verilog/dv/harness/sections.lds
@@ -1,6 +1,6 @@
 MEMORY {
 	FLASH (rx)	: ORIGIN = 0x10000000, LENGTH = 0x400000 	/* 4MB */
-	RAM(xrw)	: ORIGIN = 0x00000000, LENGTH = 0x400		/* 256 words ( 1024 ? ) */ 
+	RAM(xrw)	: ORIGIN = 0x00000000, LENGTH = 0x8000		/* 8192 words ( 32 KB) */ 
 }
 
 SECTIONS {
diff --git a/verilog/dv/harness/mgmt_soc/spiflash.v b/verilog/dv/harness/spiflash.v
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/spiflash.v
rename to verilog/dv/harness/spiflash.v
diff --git a/verilog/dv/harness/mgmt_soc/start.s b/verilog/dv/harness/start.s
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/start.s
rename to verilog/dv/harness/start.s
diff --git a/verilog/dv/harness/stub.c b/verilog/dv/harness/stub.c
new file mode 100644
index 0000000..4d9c970
--- /dev/null
+++ b/verilog/dv/harness/stub.c
@@ -0,0 +1,12 @@
+void putchar(char c)
+{
+	if (c == '\n')
+		putchar('\r');
+	reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+	while (*p)
+		putchar(*(p++));
+}
\ No newline at end of file
diff --git a/verilog/dv/harness/mgmt_soc/tbuart.v b/verilog/dv/harness/tbuart.v
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/tbuart.v
rename to verilog/dv/harness/tbuart.v
diff --git a/verilog/dv/harness/mgmt_soc/verify.log b/verilog/dv/harness/verify.log
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/verify.log
rename to verilog/dv/harness/verify.log