diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index a39fdea..3e92b15 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -41,7 +41,6 @@
 `include "housekeeping_spi.v"
 `include "digital_pll.v"
 `include "caravel_clkrst.v"
-`include "mprj_counter.v"
 `include "mgmt_core.v"
 `include "mprj_io.v"
 `include "chip_io.v"
@@ -49,6 +48,11 @@
 `include "gpio_control_block.v"
 `include "simple_por.v"
 
+/*------------------------------*/
+/* Include user project here	*/
+/*------------------------------*/
+`include "user_proj_example.v"
+
 `ifdef USE_OPENRAM
     `include "sram_1rw1r_32_8192_8_sky130.v"
 `endif
@@ -352,7 +356,11 @@
 		.TE_B(la_oen)
 	);
 	
-	mega_project mprj ( 
+	/*--------------------------------------*/
+	/* User project is instantiated  here	*/
+	/*--------------------------------------*/
+
+	user_proj_example mprj ( 
     		.wb_clk_i(caravel_clk),
     		.wb_rst_i(!caravel_rstn),
 		// MGMT SoC Wishbone Slave 
@@ -369,10 +377,14 @@
 		.la_data_out(la_data_out_mprj),
 		.la_oen (la_oen),
 		// IO Pads
-		.io_in (mprj_io_in),
-    		.io_out()		// ???
+		.io_in (user_io_in),
+    		.io_out(user_io_out)
 	);
 
+	/*--------------------------------------*/
+	/* End user project instantiation	*/
+	/*--------------------------------------*/
+
     wire [`MPRJ_IO_PADS-1:0] gpio_serial_link_shifted;
 
     assign gpio_serial_link_shifted = {gpio_serial_link[`MPRJ_IO_PADS-2:0], mprj_io_loader_data};
diff --git a/verilog/rtl/mprj_ctrl.v.orig b/verilog/rtl/mprj_ctrl.v.orig
deleted file mode 100644
index 35fc346..0000000
--- a/verilog/rtl/mprj_ctrl.v.orig
+++ /dev/null
@@ -1,283 +0,0 @@
-module mprj_ctrl_wb #(
-    parameter BASE_ADR = 32'h 2300_0000,
-    parameter DATA   = 8'h 00,
-    parameter XFER   = 8'h 04,
-    parameter CONFIG = 8'h 08,
-    parameter IO_PADS = 32,   // Number of IO control registers
-    parameter PWR_PADS = 32   // Number of power control registers
-)(
-    input wb_clk_i,
-    input wb_rst_i,
-
-    input [31:0] wb_dat_i,
-    input [31:0] wb_adr_i,
-    input [3:0] wb_sel_i,
-    input wb_cyc_i,
-    input wb_stb_i,
-    input wb_we_i,
-
-    output [31:0] wb_dat_o,
-    output wb_ack_o,
-
-    // Output is to serial loader
-    output serial_clock,
-    output serial_resetn,
-    output serial_data_out,
-
-    // Read/write data to each GPIO pad from management SoC
-    inout [IO_PADS-1:0] mgmt_gpio_io
-);
-    wire resetn;
-    wire valid;
-    wire ready;
-    wire [3:0] iomem_we;
-
-    assign resetn = ~wb_rst_i;
-    assign valid  = wb_stb_i && wb_cyc_i; 
-
-    assign iomem_we = wb_sel_i & {4{wb_we_i}};
-    assign wb_ack_o = ready;
-
-    mprj_ctrl #(
-        .BASE_ADR(BASE_ADR),
-	.DATA(DATA),
-        .CONFIG(CONFIG),
-        .XFER(XFER),
-	.IO_PADS(IO_PADS),
-        .PWR_PADS(PWR_PADS)
-    ) mprj_ctrl (
-        .clk(wb_clk_i),
-        .resetn(resetn),
-        .iomem_addr(wb_adr_i),
-        .iomem_valid(valid),
-        .iomem_wstrb(iomem_we[1:0]),
-        .iomem_wdata(wb_dat_i),
-        .iomem_rdata(wb_dat_o),
-        .iomem_ready(ready),
-
-	.serial_clock(serial_clock),
-	.serial_resetn(serial_resetn),
-	.serial_data_out(serial_data_out),
-	.mgmt_gpio_io(mgmt_gpio_io)
-    );
-
-endmodule
-
-module mprj_ctrl #(
-    parameter BASE_ADR = 32'h 2300_0000,
-    parameter DATA   = 8'h 00,
-    parameter XFER   = 8'h 04,
-    parameter CONFIG = 8'h 08,
-    parameter IO_PADS = 32,
-    parameter PWR_PADS = 32,
-    parameter IO_CTRL_BITS = 14,
-    parameter PWR_CTRL_BITS = 1
-)(
-    input clk,
-    input resetn,
-
-    input [31:0] iomem_addr,
-    input iomem_valid,
-    input [1:0] iomem_wstrb,
-    input [31:0] iomem_wdata,
-    output reg [31:0] iomem_rdata,
-    output reg iomem_ready,
-
-    output serial_clock,
-    output serial_resetn,
-    output serial_data_out,
-    inout [IO_PADS-1:0] mgmt_gpio_io
-);
-
-`define IDLE	2'b00
-`define START	2'b01
-`define XBYTE	2'b10
-`define LOAD	2'b11
-
-    localparam IO_BASE_ADR = (BASE_ADR | CONFIG);
-    localparam PWR_BASE_ADR = (BASE_ADR | CONFIG) + IO_PADS*4;
-    localparam OEB = 1;			// Offset of OEB in shift register block.
-
-    reg [IO_CTRL_BITS-1:0] io_ctrl [IO_PADS-1:0];  // I/O control, 1 word per gpio pad
-    reg [PWR_CTRL_BITS-1:0] pwr_ctrl [PWR_PADS-1:0];// Power control, 1 word per power pad
-    reg [IO_PADS-1:0] mgmt_gpio_out;	// I/O read/write data, 1 bit per gpio pad
-    reg xfer_ctrl;			// Transfer control (1 bit)
-
-    wire [IO_PADS-1:0] io_ctrl_sel;	// wishbone selects
-    wire [PWR_PADS-1:0] pwr_ctrl_sel;
-    wire io_data_sel;
-    wire xfer_sel;
-    wire [IO_PADS-1:0] mgmt_gpio_in;
-
-    assign xfer_sel = (iomem_addr[7:0] == XFER);
-    assign io_data_sel = (iomem_addr[7:0] == DATA); 
-
-    // Direction of mgmt_gpio_io depends on the value of io_ctrl pad bit 1 (OEB)
-    // if OEB = 0 then mgmt_gpio_out --> mgmt_gpio_io;  if OEB = 1 then
-    // mgmt_gpio_io --> mgmt_gpio_in.  mgmt_gpio_in is always a copy of mgmt_gpio_io.
-
-    assign mgmt_gpio_in = mgmt_gpio_io;
-
-    genvar i;
-    generate
-        for (i=0; i<IO_PADS; i=i+1) begin
-            assign io_ctrl_sel[i] = (iomem_addr[7:0] == (IO_BASE_ADR[7:0] + i*4)); 
-            assign mgmt_gpio_io[i] = (io_ctrl[0][i] + OEB == 1'b0) ?
-				mgmt_gpio_out[i] : 1'bz;
-        end
-    endgenerate
-
-    generate
-        for (i=0; i<PWR_PADS; i=i+1) begin
-            assign pwr_ctrl_sel[i] = (iomem_addr[7:0] == (PWR_BASE_ADR[7:0] + i*4)); 
-        end
-    endgenerate
-
-    // I/O transfer of xfer bit and gpio data to/from user project region under
-    // management SoC control
-
-    always @(posedge clk) begin
-	if (!resetn) begin
-	    xfer_ctrl <= 0;
-	    mgmt_gpio_out <= 'd0;
-	end else begin
-	    iomem_ready <= 0;
-	    if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
-		iomem_ready <= 1'b 1;
-
-		if (io_data_sel) begin
-		    iomem_rdata <= mgmt_gpio_in;
-		    mgmt_gpio_out <= 'd0;
-		    if (iomem_wstrb[0]) mgmt_gpio_out[IO_PADS-1:0] <= iomem_wdata[IO_PADS-1:0];
-
-		end else if (xfer_sel) begin
-		    iomem_rdata <= {31'd0, xfer_ctrl};
-		    if (iomem_wstrb[0]) xfer_ctrl <= iomem_wdata[1:0];
-		end
-	    end
-	end
-    end
-
-    generate 
-        for (i=0; i<IO_PADS; i=i+1) begin
-             always @(posedge clk) begin
-                if (!resetn) begin
-		    // NOTE:  This needs to be set to the specific bit sequence
-		    // that initializes every I/O pad to the appropriate state on
-		    // startup.
-                    io_ctrl[i] <= 'd0;
-                end else begin
-                    if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
-                        if (io_ctrl_sel[i]) begin
-                            iomem_rdata <= io_ctrl[i];
-			    // NOTE:  Byte-wide write to io_ctrl is prohibited
-                            if (iomem_wstrb[0])
-				io_ctrl[i] <= iomem_wdata[IO_CTRL_BITS-1:0];
-                        end 
-                    end
-                end
-            end
-        end
-    endgenerate
-
-    generate 
-        for (i=0; i<PWR_PADS; i=i+1) begin
-             always @(posedge clk) begin
-                if (!resetn) begin
-                    pwr_ctrl[i] <= 'd0;
-                end else begin
-                    if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
-                        if (pwr_ctrl_sel[i]) begin
-                            iomem_rdata <= pwr_ctrl[i];
-                            if (iomem_wstrb[0])
-				pwr_ctrl[i] <= iomem_wdata[PWR_CTRL_BITS-1:0];
-                        end 
-                    end
-                end
-            end
-        end
-    endgenerate
-
-    reg [3:0]  xfer_count;
-    reg [5:0]  pad_count;
-    reg [1:0]  xfer_state;
-    reg	       serial_clock;
-    reg	       serial_resetn;
-    reg	       serial_data_out;
-
-    // NOTE:  Ignoring power control bits for now. . .  need to revisit.
-    // Depends on how the power pads are arranged among the GPIO, and
-    // whether or not switching will be internal and under the control
-    // of the SoC.
-
-    reg [IO_CTRL_BITS-1:0] serial_data_staging;
-
-    always @(posedge clk or negedge resetn) begin
-	if (resetn == 1'b0) begin
-
-	    xfer_state <= `IDLE;
-	    xfer_count <= 4'd0;
-	    pad_count  <= 6'd0;
-	    serial_resetn <= 1'b0;
-	    serial_clock <= 1'b0;
-	    serial_data_out <= 1'b0;
-
-	end else begin
-
-	    if (xfer_state == `IDLE) begin
-	    	serial_resetn <= 1'b0;
-		serial_clock <= 1'b0;
-		if (xfer_ctrl == 1'b1) begin
-		    xfer_state <= `START;
-		end
-	    end else if (xfer_state == `START) begin
-	    	serial_resetn <= 1'b1;
-		serial_clock <= 1'b0;
-	    	xfer_count <= 6'd0;
-		if (pad_count == IO_PADS) begin
-		    xfer_state <= `LOAD;
-		end else begin
-		    pad_count <= pad_count + 1;
-		    xfer_state <= `XBYTE;
-		    serial_data_staging <= io_ctrl[pad_count];
-		end
-	    end else if (xfer_state == `XBYTE) begin
-	    	serial_resetn <= 1'b1;
-		serial_clock <= ~serial_clock;
-		if (serial_clock == 1'b0) begin
-		    if (xfer_count == IO_CTRL_BITS) begin
-		    	xfer_state <= `START;
-		    end else begin
-		    	xfer_count <= xfer_count + 1;
-		    end
-		end else begin
-		    serial_data_staging <= {serial_data_staging[IO_CTRL_BITS-2:0], 1'b0};
-		    serial_data_out <= serial_data_staging[IO_CTRL_BITS-1];
-		end
-	    end else if (xfer_state == `LOAD) begin
-		xfer_count <= xfer_count + 1;
-
-		/* Load sequence:  Raise clock for final data shift in;
-		 * Pulse reset low while clock is high
-		 * Set clock back to zero.
-		 * Return to idle mode.
-		 */
-		if (xfer_count == 4'd0) begin
-		    serial_clock <= 1'b1;
-		    serial_resetn <= 1'b1;
-		end else if (xfer_count == 4'd1) begin
-		    serial_clock <= 1'b1;
-		    serial_resetn <= 1'b0;
-		end else if (xfer_count == 4'd2) begin
-		    serial_clock <= 1'b1;
-		    serial_resetn <= 1'b1;
-		end else if (xfer_count == 4'd3) begin
-		    serial_resetn <= 1'b1;
-		    serial_clock <= 1'b0;
-		    xfer_state <= `IDLE;
-		end
-	    end	
-	end
-    end
-
-endmodule
diff --git a/verilog/rtl/mprj_counter.v b/verilog/rtl/user_proj_example.v
similarity index 75%
rename from verilog/rtl/mprj_counter.v
rename to verilog/rtl/user_proj_example.v
index 924a52c..af198c4 100644
--- a/verilog/rtl/mprj_counter.v
+++ b/verilog/rtl/user_proj_example.v
@@ -1,22 +1,45 @@
-module mega_project #(
+/*
+ *-------------------------------------------------------------
+ *
+ * user_proj_example
+ *
+ * This is an example of a (trivially simple) user project,
+ * showing how the user project can connect to the logic
+ * analyzer, the wishbone bus, and the I/O pads.
+ *
+ * This project generates an integer count, which is output
+ * on the user area GPIO pads (digital output only).  The
+ * wishbone connection allows the project to be controlled
+ * (start and stop) from the management SoC program.
+ *
+ * See the testbenches in directory "mprj_counter" for the
+ * example programs that drive this user project.  The three
+ * testbenches are "io_ports", "la_test1", and "la_test2".
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_proj_example #(
     parameter IO_PADS = 32,
     parameter BITS = 32
 )(
     // Wishbone Slave ports (WB MI A)
     input wb_clk_i,
     input wb_rst_i,
-	input wbs_stb_i,
-	input wbs_cyc_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
     input wbs_we_i,
-	input [3:0] wbs_sel_i,
+    input [3:0] wbs_sel_i,
     input [31:0] wbs_dat_i,
     input [31:0] wbs_adr_i,
     output wbs_ack_o,
-	output [31:0] wbs_dat_o,
+    output [31:0] wbs_dat_o,
+
     // Logic Analyzer Signals
     input  [127:0] la_data_in,
     output [127:0] la_data_out,
     input  [127:0] la_oen,
+
     // IOs
     input  [IO_PADS-1:0] io_in,
     output [IO_PADS-1:0] io_out
@@ -113,4 +136,4 @@
         end
     endgenerate
 
-endmodule
\ No newline at end of file
+endmodule