)]}'
{
  "commit": "0445c08e6ae05805b5a8cb8319bbd3c321a04225",
  "tree": "51ccdb87f9d2869814ee1dc424ce40ecf19b17e0",
  "parents": [
    "ba3289096e696a0449bb485d8a28f8559fa3066a"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Tue Oct 27 20:53:54 2020 -0400"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Oct 28 22:58:29 2020 +0200"
  },
  "message": "Revised the mprj_ctrl module verilog so that it does not generate\nconflicting drivers for the register input from the viewpoint of the\nsynthesis tools.  Updated the testbench to remove references to the\n\"mega-project\", and made a few updates to the datasheet.\n",
  "tree_diff": [
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      "new_path": "doc/caravel_datasheet.pdf"
    },
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}