| module ibex_controller ( |
| clk_i, |
| rst_ni, |
| ctrl_busy_o, |
| illegal_insn_i, |
| ecall_insn_i, |
| mret_insn_i, |
| dret_insn_i, |
| wfi_insn_i, |
| ebrk_insn_i, |
| csr_pipe_flush_i, |
| instr_valid_i, |
| instr_i, |
| instr_compressed_i, |
| instr_is_compressed_i, |
| instr_bp_taken_i, |
| instr_fetch_err_i, |
| instr_fetch_err_plus2_i, |
| pc_id_i, |
| instr_valid_clear_o, |
| id_in_ready_o, |
| controller_run_o, |
| instr_req_o, |
| pc_set_o, |
| pc_set_spec_o, |
| pc_mux_o, |
| nt_branch_mispredict_o, |
| exc_pc_mux_o, |
| exc_cause_o, |
| lsu_addr_last_i, |
| load_err_i, |
| store_err_i, |
| wb_exception_o, |
| branch_set_i, |
| branch_set_spec_i, |
| branch_not_set_i, |
| jump_set_i, |
| csr_mstatus_mie_i, |
| irq_pending_i, |
| irqs_i, |
| irq_nm_i, |
| nmi_mode_o, |
| debug_req_i, |
| debug_cause_o, |
| debug_csr_save_o, |
| debug_mode_o, |
| debug_single_step_i, |
| debug_ebreakm_i, |
| debug_ebreaku_i, |
| trigger_match_i, |
| csr_save_if_o, |
| csr_save_id_o, |
| csr_save_wb_o, |
| csr_restore_mret_id_o, |
| csr_restore_dret_id_o, |
| csr_save_cause_o, |
| csr_mtval_o, |
| priv_mode_i, |
| csr_mstatus_tw_i, |
| stall_id_i, |
| stall_wb_i, |
| flush_id_o, |
| ready_wb_i, |
| perf_jump_o, |
| perf_tbranch_o |
| ); |
| parameter [0:0] WritebackStage = 0; |
| parameter [0:0] BranchPredictor = 0; |
| input wire clk_i; |
| input wire rst_ni; |
| output reg ctrl_busy_o; |
| input wire illegal_insn_i; |
| input wire ecall_insn_i; |
| input wire mret_insn_i; |
| input wire dret_insn_i; |
| input wire wfi_insn_i; |
| input wire ebrk_insn_i; |
| input wire csr_pipe_flush_i; |
| input wire instr_valid_i; |
| input wire [31:0] instr_i; |
| input wire [15:0] instr_compressed_i; |
| input wire instr_is_compressed_i; |
| input wire instr_bp_taken_i; |
| input wire instr_fetch_err_i; |
| input wire instr_fetch_err_plus2_i; |
| input wire [31:0] pc_id_i; |
| output wire instr_valid_clear_o; |
| output wire id_in_ready_o; |
| output reg controller_run_o; |
| output reg instr_req_o; |
| output reg pc_set_o; |
| output reg pc_set_spec_o; |
| output reg [2:0] pc_mux_o; |
| output reg nt_branch_mispredict_o; |
| output reg [1:0] exc_pc_mux_o; |
| output reg [5:0] exc_cause_o; |
| input wire [31:0] lsu_addr_last_i; |
| input wire load_err_i; |
| input wire store_err_i; |
| output wire wb_exception_o; |
| input wire branch_set_i; |
| input wire branch_set_spec_i; |
| input wire branch_not_set_i; |
| input wire jump_set_i; |
| input wire csr_mstatus_mie_i; |
| input wire irq_pending_i; |
| input wire [17:0] irqs_i; |
| input wire irq_nm_i; |
| output wire nmi_mode_o; |
| input wire debug_req_i; |
| output reg [2:0] debug_cause_o; |
| output reg debug_csr_save_o; |
| output wire debug_mode_o; |
| input wire debug_single_step_i; |
| input wire debug_ebreakm_i; |
| input wire debug_ebreaku_i; |
| input wire trigger_match_i; |
| output reg csr_save_if_o; |
| output reg csr_save_id_o; |
| output reg csr_save_wb_o; |
| output reg csr_restore_mret_id_o; |
| output reg csr_restore_dret_id_o; |
| output reg csr_save_cause_o; |
| output reg [31:0] csr_mtval_o; |
| input wire [1:0] priv_mode_i; |
| input wire csr_mstatus_tw_i; |
| input wire stall_id_i; |
| input wire stall_wb_i; |
| output wire flush_id_o; |
| input wire ready_wb_i; |
| output reg perf_jump_o; |
| output reg perf_tbranch_o; |
| localparam integer RegFileFF = 0; |
| localparam integer RegFileFPGA = 1; |
| localparam integer RegFileLatch = 2; |
| localparam integer RV32MNone = 0; |
| localparam integer RV32MSlow = 1; |
| localparam integer RV32MFast = 2; |
| localparam integer RV32MSingleCycle = 3; |
| localparam integer RV32BNone = 0; |
| localparam integer RV32BBalanced = 1; |
| localparam integer RV32BFull = 2; |
| localparam [6:0] OPCODE_LOAD = 7'h03; |
| localparam [6:0] OPCODE_MISC_MEM = 7'h0f; |
| localparam [6:0] OPCODE_OP_IMM = 7'h13; |
| localparam [6:0] OPCODE_AUIPC = 7'h17; |
| localparam [6:0] OPCODE_STORE = 7'h23; |
| localparam [6:0] OPCODE_OP = 7'h33; |
| localparam [6:0] OPCODE_LUI = 7'h37; |
| localparam [6:0] OPCODE_BRANCH = 7'h63; |
| localparam [6:0] OPCODE_JALR = 7'h67; |
| localparam [6:0] OPCODE_JAL = 7'h6f; |
| localparam [6:0] OPCODE_SYSTEM = 7'h73; |
| localparam [5:0] ALU_ADD = 0; |
| localparam [5:0] ALU_SUB = 1; |
| localparam [5:0] ALU_XOR = 2; |
| localparam [5:0] ALU_OR = 3; |
| localparam [5:0] ALU_AND = 4; |
| localparam [5:0] ALU_XNOR = 5; |
| localparam [5:0] ALU_ORN = 6; |
| localparam [5:0] ALU_ANDN = 7; |
| localparam [5:0] ALU_SRA = 8; |
| localparam [5:0] ALU_SRL = 9; |
| localparam [5:0] ALU_SLL = 10; |
| localparam [5:0] ALU_SRO = 11; |
| localparam [5:0] ALU_SLO = 12; |
| localparam [5:0] ALU_ROR = 13; |
| localparam [5:0] ALU_ROL = 14; |
| localparam [5:0] ALU_GREV = 15; |
| localparam [5:0] ALU_GORC = 16; |
| localparam [5:0] ALU_SHFL = 17; |
| localparam [5:0] ALU_UNSHFL = 18; |
| localparam [5:0] ALU_LT = 19; |
| localparam [5:0] ALU_LTU = 20; |
| localparam [5:0] ALU_GE = 21; |
| localparam [5:0] ALU_GEU = 22; |
| localparam [5:0] ALU_EQ = 23; |
| localparam [5:0] ALU_NE = 24; |
| localparam [5:0] ALU_MIN = 25; |
| localparam [5:0] ALU_MINU = 26; |
| localparam [5:0] ALU_MAX = 27; |
| localparam [5:0] ALU_MAXU = 28; |
| localparam [5:0] ALU_PACK = 29; |
| localparam [5:0] ALU_PACKU = 30; |
| localparam [5:0] ALU_PACKH = 31; |
| localparam [5:0] ALU_SEXTB = 32; |
| localparam [5:0] ALU_SEXTH = 33; |
| localparam [5:0] ALU_CLZ = 34; |
| localparam [5:0] ALU_CTZ = 35; |
| localparam [5:0] ALU_PCNT = 36; |
| localparam [5:0] ALU_SLT = 37; |
| localparam [5:0] ALU_SLTU = 38; |
| localparam [5:0] ALU_CMOV = 39; |
| localparam [5:0] ALU_CMIX = 40; |
| localparam [5:0] ALU_FSL = 41; |
| localparam [5:0] ALU_FSR = 42; |
| localparam [5:0] ALU_SBSET = 43; |
| localparam [5:0] ALU_SBCLR = 44; |
| localparam [5:0] ALU_SBINV = 45; |
| localparam [5:0] ALU_SBEXT = 46; |
| localparam [5:0] ALU_BEXT = 47; |
| localparam [5:0] ALU_BDEP = 48; |
| localparam [5:0] ALU_BFP = 49; |
| localparam [5:0] ALU_CLMUL = 50; |
| localparam [5:0] ALU_CLMULR = 51; |
| localparam [5:0] ALU_CLMULH = 52; |
| localparam [5:0] ALU_CRC32_B = 53; |
| localparam [5:0] ALU_CRC32C_B = 54; |
| localparam [5:0] ALU_CRC32_H = 55; |
| localparam [5:0] ALU_CRC32C_H = 56; |
| localparam [5:0] ALU_CRC32_W = 57; |
| localparam [5:0] ALU_CRC32C_W = 58; |
| localparam [1:0] MD_OP_MULL = 0; |
| localparam [1:0] MD_OP_MULH = 1; |
| localparam [1:0] MD_OP_DIV = 2; |
| localparam [1:0] MD_OP_REM = 3; |
| localparam [1:0] CSR_OP_READ = 0; |
| localparam [1:0] CSR_OP_WRITE = 1; |
| localparam [1:0] CSR_OP_SET = 2; |
| localparam [1:0] CSR_OP_CLEAR = 3; |
| localparam [1:0] PRIV_LVL_M = 2'b11; |
| localparam [1:0] PRIV_LVL_H = 2'b10; |
| localparam [1:0] PRIV_LVL_S = 2'b01; |
| localparam [1:0] PRIV_LVL_U = 2'b00; |
| localparam [3:0] XDEBUGVER_NO = 4'd0; |
| localparam [3:0] XDEBUGVER_STD = 4'd4; |
| localparam [3:0] XDEBUGVER_NONSTD = 4'd15; |
| localparam [1:0] WB_INSTR_LOAD = 0; |
| localparam [1:0] WB_INSTR_STORE = 1; |
| localparam [1:0] WB_INSTR_OTHER = 2; |
| localparam [1:0] OP_A_REG_A = 0; |
| localparam [1:0] OP_A_FWD = 1; |
| localparam [1:0] OP_A_CURRPC = 2; |
| localparam [1:0] OP_A_IMM = 3; |
| localparam [0:0] IMM_A_Z = 0; |
| localparam [0:0] IMM_A_ZERO = 1; |
| localparam [0:0] OP_B_REG_B = 0; |
| localparam [0:0] OP_B_IMM = 1; |
| localparam [2:0] IMM_B_I = 0; |
| localparam [2:0] IMM_B_S = 1; |
| localparam [2:0] IMM_B_B = 2; |
| localparam [2:0] IMM_B_U = 3; |
| localparam [2:0] IMM_B_J = 4; |
| localparam [2:0] IMM_B_INCR_PC = 5; |
| localparam [2:0] IMM_B_INCR_ADDR = 6; |
| localparam [0:0] RF_WD_EX = 0; |
| localparam [0:0] RF_WD_CSR = 1; |
| localparam [2:0] PC_BOOT = 0; |
| localparam [2:0] PC_JUMP = 1; |
| localparam [2:0] PC_EXC = 2; |
| localparam [2:0] PC_ERET = 3; |
| localparam [2:0] PC_DRET = 4; |
| localparam [2:0] PC_BP = 5; |
| localparam [1:0] EXC_PC_EXC = 0; |
| localparam [1:0] EXC_PC_IRQ = 1; |
| localparam [1:0] EXC_PC_DBD = 2; |
| localparam [1:0] EXC_PC_DBG_EXC = 3; |
| localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; |
| localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; |
| localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; |
| localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; |
| localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; |
| localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; |
| localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; |
| localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; |
| localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; |
| localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; |
| localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; |
| localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; |
| localparam [2:0] DBG_CAUSE_NONE = 3'h0; |
| localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; |
| localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; |
| localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; |
| localparam [2:0] DBG_CAUSE_STEP = 3'h4; |
| localparam [31:0] PMP_MAX_REGIONS = 16; |
| localparam [31:0] PMP_CFG_W = 8; |
| localparam [31:0] PMP_I = 0; |
| localparam [31:0] PMP_D = 1; |
| localparam [1:0] PMP_ACC_EXEC = 2'b00; |
| localparam [1:0] PMP_ACC_WRITE = 2'b01; |
| localparam [1:0] PMP_ACC_READ = 2'b10; |
| localparam [1:0] PMP_MODE_OFF = 2'b00; |
| localparam [1:0] PMP_MODE_TOR = 2'b01; |
| localparam [1:0] PMP_MODE_NA4 = 2'b10; |
| localparam [1:0] PMP_MODE_NAPOT = 2'b11; |
| localparam [11:0] CSR_MHARTID = 12'hf14; |
| localparam [11:0] CSR_MSTATUS = 12'h300; |
| localparam [11:0] CSR_MISA = 12'h301; |
| localparam [11:0] CSR_MIE = 12'h304; |
| localparam [11:0] CSR_MTVEC = 12'h305; |
| localparam [11:0] CSR_MSCRATCH = 12'h340; |
| localparam [11:0] CSR_MEPC = 12'h341; |
| localparam [11:0] CSR_MCAUSE = 12'h342; |
| localparam [11:0] CSR_MTVAL = 12'h343; |
| localparam [11:0] CSR_MIP = 12'h344; |
| localparam [11:0] CSR_PMPCFG0 = 12'h3a0; |
| localparam [11:0] CSR_PMPCFG1 = 12'h3a1; |
| localparam [11:0] CSR_PMPCFG2 = 12'h3a2; |
| localparam [11:0] CSR_PMPCFG3 = 12'h3a3; |
| localparam [11:0] CSR_PMPADDR0 = 12'h3b0; |
| localparam [11:0] CSR_PMPADDR1 = 12'h3b1; |
| localparam [11:0] CSR_PMPADDR2 = 12'h3b2; |
| localparam [11:0] CSR_PMPADDR3 = 12'h3b3; |
| localparam [11:0] CSR_PMPADDR4 = 12'h3b4; |
| localparam [11:0] CSR_PMPADDR5 = 12'h3b5; |
| localparam [11:0] CSR_PMPADDR6 = 12'h3b6; |
| localparam [11:0] CSR_PMPADDR7 = 12'h3b7; |
| localparam [11:0] CSR_PMPADDR8 = 12'h3b8; |
| localparam [11:0] CSR_PMPADDR9 = 12'h3b9; |
| localparam [11:0] CSR_PMPADDR10 = 12'h3ba; |
| localparam [11:0] CSR_PMPADDR11 = 12'h3bb; |
| localparam [11:0] CSR_PMPADDR12 = 12'h3bc; |
| localparam [11:0] CSR_PMPADDR13 = 12'h3bd; |
| localparam [11:0] CSR_PMPADDR14 = 12'h3be; |
| localparam [11:0] CSR_PMPADDR15 = 12'h3bf; |
| localparam [11:0] CSR_TSELECT = 12'h7a0; |
| localparam [11:0] CSR_TDATA1 = 12'h7a1; |
| localparam [11:0] CSR_TDATA2 = 12'h7a2; |
| localparam [11:0] CSR_TDATA3 = 12'h7a3; |
| localparam [11:0] CSR_MCONTEXT = 12'h7a8; |
| localparam [11:0] CSR_SCONTEXT = 12'h7aa; |
| localparam [11:0] CSR_DCSR = 12'h7b0; |
| localparam [11:0] CSR_DPC = 12'h7b1; |
| localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; |
| localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; |
| localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; |
| localparam [11:0] CSR_MHPMEVENT3 = 12'h323; |
| localparam [11:0] CSR_MHPMEVENT4 = 12'h324; |
| localparam [11:0] CSR_MHPMEVENT5 = 12'h325; |
| localparam [11:0] CSR_MHPMEVENT6 = 12'h326; |
| localparam [11:0] CSR_MHPMEVENT7 = 12'h327; |
| localparam [11:0] CSR_MHPMEVENT8 = 12'h328; |
| localparam [11:0] CSR_MHPMEVENT9 = 12'h329; |
| localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; |
| localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; |
| localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; |
| localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; |
| localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; |
| localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; |
| localparam [11:0] CSR_MHPMEVENT16 = 12'h330; |
| localparam [11:0] CSR_MHPMEVENT17 = 12'h331; |
| localparam [11:0] CSR_MHPMEVENT18 = 12'h332; |
| localparam [11:0] CSR_MHPMEVENT19 = 12'h333; |
| localparam [11:0] CSR_MHPMEVENT20 = 12'h334; |
| localparam [11:0] CSR_MHPMEVENT21 = 12'h335; |
| localparam [11:0] CSR_MHPMEVENT22 = 12'h336; |
| localparam [11:0] CSR_MHPMEVENT23 = 12'h337; |
| localparam [11:0] CSR_MHPMEVENT24 = 12'h338; |
| localparam [11:0] CSR_MHPMEVENT25 = 12'h339; |
| localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; |
| localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; |
| localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; |
| localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; |
| localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; |
| localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; |
| localparam [11:0] CSR_MCYCLE = 12'hb00; |
| localparam [11:0] CSR_MINSTRET = 12'hb02; |
| localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; |
| localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; |
| localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; |
| localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; |
| localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; |
| localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; |
| localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; |
| localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; |
| localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; |
| localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; |
| localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; |
| localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; |
| localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; |
| localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; |
| localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; |
| localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; |
| localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; |
| localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; |
| localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; |
| localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; |
| localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; |
| localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; |
| localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; |
| localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; |
| localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; |
| localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; |
| localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; |
| localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; |
| localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; |
| localparam [11:0] CSR_MCYCLEH = 12'hb80; |
| localparam [11:0] CSR_MINSTRETH = 12'hb82; |
| localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; |
| localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; |
| localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; |
| localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; |
| localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; |
| localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; |
| localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; |
| localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; |
| localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; |
| localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; |
| localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; |
| localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; |
| localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; |
| localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; |
| localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; |
| localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; |
| localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; |
| localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; |
| localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; |
| localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; |
| localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; |
| localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; |
| localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; |
| localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; |
| localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; |
| localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; |
| localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; |
| localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; |
| localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; |
| localparam [11:0] CSR_CPUCTRL = 12'h7c0; |
| localparam [11:0] CSR_SECURESEED = 12'h7c1; |
| localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; |
| localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; |
| localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; |
| localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; |
| localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; |
| localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; |
| localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; |
| localparam [31:0] CSR_MSTATUS_TW_BIT = 21; |
| localparam [1:0] CSR_MISA_MXL = 2'd1; |
| localparam [31:0] CSR_MSIX_BIT = 3; |
| localparam [31:0] CSR_MTIX_BIT = 7; |
| localparam [31:0] CSR_MEIX_BIT = 11; |
| localparam [31:0] CSR_MFIX_BIT_LOW = 16; |
| localparam [31:0] CSR_MFIX_BIT_HIGH = 30; |
| reg [3:0] ctrl_fsm_cs; |
| reg [3:0] ctrl_fsm_ns; |
| reg nmi_mode_q; |
| reg nmi_mode_d; |
| reg debug_mode_q; |
| reg debug_mode_d; |
| reg load_err_q; |
| wire load_err_d; |
| reg store_err_q; |
| wire store_err_d; |
| reg exc_req_q; |
| wire exc_req_d; |
| reg illegal_insn_q; |
| wire illegal_insn_d; |
| reg instr_fetch_err_prio; |
| reg illegal_insn_prio; |
| reg ecall_insn_prio; |
| reg ebrk_insn_prio; |
| reg store_err_prio; |
| reg load_err_prio; |
| wire stall; |
| reg halt_if; |
| reg retain_id; |
| reg flush_id; |
| wire illegal_dret; |
| wire illegal_umode; |
| wire exc_req_lsu; |
| wire special_req_all; |
| wire special_req_branch; |
| wire enter_debug_mode; |
| wire ebreak_into_debug; |
| wire handle_irq; |
| reg [3:0] mfip_id; |
| wire unused_irq_timer; |
| wire ecall_insn; |
| wire mret_insn; |
| wire dret_insn; |
| wire wfi_insn; |
| wire ebrk_insn; |
| wire csr_pipe_flush; |
| wire instr_fetch_err; |
| assign load_err_d = load_err_i; |
| assign store_err_d = store_err_i; |
| assign ecall_insn = ecall_insn_i & instr_valid_i; |
| assign mret_insn = mret_insn_i & instr_valid_i; |
| assign dret_insn = dret_insn_i & instr_valid_i; |
| assign wfi_insn = wfi_insn_i & instr_valid_i; |
| assign ebrk_insn = ebrk_insn_i & instr_valid_i; |
| assign csr_pipe_flush = csr_pipe_flush_i & instr_valid_i; |
| assign instr_fetch_err = instr_fetch_err_i & instr_valid_i; |
| assign illegal_dret = dret_insn & ~debug_mode_q; |
| assign illegal_umode = (priv_mode_i != PRIV_LVL_M) & (mret_insn | (csr_mstatus_tw_i & wfi_insn)); |
| localparam [3:0] FLUSH = 6; |
| assign illegal_insn_d = ((illegal_insn_i | illegal_dret) | illegal_umode) & (ctrl_fsm_cs != FLUSH); |
| assign exc_req_d = (((ecall_insn | ebrk_insn) | illegal_insn_d) | instr_fetch_err) & (ctrl_fsm_cs != FLUSH); |
| assign exc_req_lsu = store_err_i | load_err_i; |
| assign special_req_all = ((((mret_insn | dret_insn) | wfi_insn) | csr_pipe_flush) | exc_req_d) | exc_req_lsu; |
| assign special_req_branch = instr_fetch_err & (ctrl_fsm_cs != FLUSH); |
| generate |
| if (WritebackStage) begin : g_wb_exceptions |
| always @(*) begin |
| instr_fetch_err_prio = 0; |
| illegal_insn_prio = 0; |
| ecall_insn_prio = 0; |
| ebrk_insn_prio = 0; |
| store_err_prio = 0; |
| load_err_prio = 0; |
| if (store_err_q) |
| store_err_prio = 1'b1; |
| else if (load_err_q) |
| load_err_prio = 1'b1; |
| else if (instr_fetch_err) |
| instr_fetch_err_prio = 1'b1; |
| else if (illegal_insn_q) |
| illegal_insn_prio = 1'b1; |
| else if (ecall_insn) |
| ecall_insn_prio = 1'b1; |
| else if (ebrk_insn) |
| ebrk_insn_prio = 1'b1; |
| end |
| assign wb_exception_o = ((load_err_q | store_err_q) | load_err_i) | store_err_i; |
| end |
| else begin : g_no_wb_exceptions |
| always @(*) begin |
| instr_fetch_err_prio = 0; |
| illegal_insn_prio = 0; |
| ecall_insn_prio = 0; |
| ebrk_insn_prio = 0; |
| store_err_prio = 0; |
| load_err_prio = 0; |
| if (instr_fetch_err) |
| instr_fetch_err_prio = 1'b1; |
| else if (illegal_insn_q) |
| illegal_insn_prio = 1'b1; |
| else if (ecall_insn) |
| ecall_insn_prio = 1'b1; |
| else if (ebrk_insn) |
| ebrk_insn_prio = 1'b1; |
| else if (store_err_q) |
| store_err_prio = 1'b1; |
| else if (load_err_q) |
| load_err_prio = 1'b1; |
| end |
| assign wb_exception_o = 1'b0; |
| end |
| endgenerate |
| assign enter_debug_mode = ((debug_req_i | (debug_single_step_i & instr_valid_i)) | trigger_match_i) & ~debug_mode_q; |
| assign ebreak_into_debug = (priv_mode_i == PRIV_LVL_M ? debug_ebreakm_i : (priv_mode_i == PRIV_LVL_U ? debug_ebreaku_i : 1'b0)); |
| assign handle_irq = (~debug_mode_q & ~nmi_mode_q) & (irq_nm_i | (irq_pending_i & csr_mstatus_mie_i)); |
| always @(*) begin : gen_mfip_id |
| if (irqs_i[14]) |
| mfip_id = 4'd14; |
| else if (irqs_i[13]) |
| mfip_id = 4'd13; |
| else if (irqs_i[12]) |
| mfip_id = 4'd12; |
| else if (irqs_i[11]) |
| mfip_id = 4'd11; |
| else if (irqs_i[10]) |
| mfip_id = 4'd10; |
| else if (irqs_i[9]) |
| mfip_id = 4'd9; |
| else if (irqs_i[8]) |
| mfip_id = 4'd8; |
| else if (irqs_i[7]) |
| mfip_id = 4'd7; |
| else if (irqs_i[6]) |
| mfip_id = 4'd6; |
| else if (irqs_i[5]) |
| mfip_id = 4'd5; |
| else if (irqs_i[4]) |
| mfip_id = 4'd4; |
| else if (irqs_i[3]) |
| mfip_id = 4'd3; |
| else if (irqs_i[2]) |
| mfip_id = 4'd2; |
| else if (irqs_i[1]) |
| mfip_id = 4'd1; |
| else |
| mfip_id = 4'd0; |
| end |
| assign unused_irq_timer = irqs_i[16]; |
| function automatic [5:0] sv2v_cast_6; |
| input reg [5:0] inp; |
| sv2v_cast_6 = inp; |
| endfunction |
| localparam [3:0] BOOT_SET = 1; |
| localparam [3:0] DBG_TAKEN_ID = 9; |
| localparam [3:0] DBG_TAKEN_IF = 8; |
| localparam [3:0] DECODE = 5; |
| localparam [3:0] FIRST_FETCH = 4; |
| localparam [3:0] IRQ_TAKEN = 7; |
| localparam [3:0] RESET = 0; |
| localparam [3:0] SLEEP = 3; |
| localparam [3:0] WAIT_SLEEP = 2; |
| always @(*) begin |
| instr_req_o = 1'b1; |
| csr_save_if_o = 1'b0; |
| csr_save_id_o = 1'b0; |
| csr_save_wb_o = 1'b0; |
| csr_restore_mret_id_o = 1'b0; |
| csr_restore_dret_id_o = 1'b0; |
| csr_save_cause_o = 1'b0; |
| csr_mtval_o = {32 {1'sb0}}; |
| pc_mux_o = PC_BOOT; |
| pc_set_o = 1'b0; |
| pc_set_spec_o = 1'b0; |
| nt_branch_mispredict_o = 1'b0; |
| exc_pc_mux_o = EXC_PC_IRQ; |
| exc_cause_o = EXC_CAUSE_INSN_ADDR_MISA; |
| ctrl_fsm_ns = ctrl_fsm_cs; |
| ctrl_busy_o = 1'b1; |
| halt_if = 1'b0; |
| retain_id = 1'b0; |
| flush_id = 1'b0; |
| debug_csr_save_o = 1'b0; |
| debug_cause_o = DBG_CAUSE_EBREAK; |
| debug_mode_d = debug_mode_q; |
| nmi_mode_d = nmi_mode_q; |
| perf_tbranch_o = 1'b0; |
| perf_jump_o = 1'b0; |
| controller_run_o = 1'b0; |
| case (ctrl_fsm_cs) |
| RESET: begin |
| instr_req_o = 1'b0; |
| pc_mux_o = PC_BOOT; |
| pc_set_o = 1'b1; |
| pc_set_spec_o = 1'b1; |
| ctrl_fsm_ns = BOOT_SET; |
| end |
| BOOT_SET: begin |
| instr_req_o = 1'b1; |
| pc_mux_o = PC_BOOT; |
| pc_set_o = 1'b1; |
| pc_set_spec_o = 1'b1; |
| ctrl_fsm_ns = FIRST_FETCH; |
| end |
| WAIT_SLEEP: begin |
| ctrl_busy_o = 1'b0; |
| instr_req_o = 1'b0; |
| halt_if = 1'b1; |
| flush_id = 1'b1; |
| ctrl_fsm_ns = SLEEP; |
| end |
| SLEEP: begin |
| instr_req_o = 1'b0; |
| halt_if = 1'b1; |
| flush_id = 1'b1; |
| if ((((irq_nm_i || irq_pending_i) || debug_req_i) || debug_mode_q) || debug_single_step_i) |
| ctrl_fsm_ns = FIRST_FETCH; |
| else |
| ctrl_busy_o = 1'b0; |
| end |
| FIRST_FETCH: begin |
| if (id_in_ready_o) |
| ctrl_fsm_ns = DECODE; |
| if (handle_irq) begin |
| ctrl_fsm_ns = IRQ_TAKEN; |
| halt_if = 1'b1; |
| end |
| if (enter_debug_mode) begin |
| ctrl_fsm_ns = DBG_TAKEN_IF; |
| halt_if = 1'b1; |
| end |
| end |
| DECODE: begin |
| controller_run_o = 1'b1; |
| pc_mux_o = PC_JUMP; |
| if (special_req_all) begin |
| retain_id = 1'b1; |
| if (ready_wb_i | wb_exception_o) |
| ctrl_fsm_ns = FLUSH; |
| end |
| if (!special_req_branch) begin |
| if (branch_set_i || jump_set_i) begin |
| pc_set_o = (BranchPredictor ? ~instr_bp_taken_i : 1'b1); |
| perf_tbranch_o = branch_set_i; |
| perf_jump_o = jump_set_i; |
| end |
| if (BranchPredictor) |
| if (instr_bp_taken_i & branch_not_set_i) |
| nt_branch_mispredict_o = 1'b1; |
| end |
| if ((branch_set_spec_i || jump_set_i) && !special_req_branch) |
| pc_set_spec_o = (BranchPredictor ? ~instr_bp_taken_i : 1'b1); |
| if ((enter_debug_mode || handle_irq) && stall) |
| halt_if = 1'b1; |
| if (!stall && !special_req_all) |
| if (enter_debug_mode) begin |
| ctrl_fsm_ns = DBG_TAKEN_IF; |
| halt_if = 1'b1; |
| end |
| else if (handle_irq) begin |
| ctrl_fsm_ns = IRQ_TAKEN; |
| halt_if = 1'b1; |
| end |
| end |
| IRQ_TAKEN: begin |
| pc_mux_o = PC_EXC; |
| exc_pc_mux_o = EXC_PC_IRQ; |
| if (handle_irq) begin |
| pc_set_o = 1'b1; |
| pc_set_spec_o = 1'b1; |
| csr_save_if_o = 1'b1; |
| csr_save_cause_o = 1'b1; |
| if (irq_nm_i && !nmi_mode_q) begin |
| exc_cause_o = EXC_CAUSE_IRQ_NM; |
| nmi_mode_d = 1'b1; |
| end |
| else if (irqs_i[14-:15] != 15'b000000000000000) |
| exc_cause_o = sv2v_cast_6({2'b11, mfip_id}); |
| else if (irqs_i[15]) |
| exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M; |
| else if (irqs_i[17]) |
| exc_cause_o = EXC_CAUSE_IRQ_SOFTWARE_M; |
| else |
| exc_cause_o = EXC_CAUSE_IRQ_TIMER_M; |
| end |
| ctrl_fsm_ns = DECODE; |
| end |
| DBG_TAKEN_IF: begin |
| pc_mux_o = PC_EXC; |
| exc_pc_mux_o = EXC_PC_DBD; |
| if ((debug_single_step_i || debug_req_i) || trigger_match_i) begin |
| flush_id = 1'b1; |
| pc_set_o = 1'b1; |
| pc_set_spec_o = 1'b1; |
| csr_save_if_o = 1'b1; |
| debug_csr_save_o = 1'b1; |
| csr_save_cause_o = 1'b1; |
| if (trigger_match_i) |
| debug_cause_o = DBG_CAUSE_TRIGGER; |
| else if (debug_single_step_i) |
| debug_cause_o = DBG_CAUSE_STEP; |
| else |
| debug_cause_o = DBG_CAUSE_HALTREQ; |
| debug_mode_d = 1'b1; |
| end |
| ctrl_fsm_ns = DECODE; |
| end |
| DBG_TAKEN_ID: begin |
| flush_id = 1'b1; |
| pc_mux_o = PC_EXC; |
| pc_set_o = 1'b1; |
| pc_set_spec_o = 1'b1; |
| exc_pc_mux_o = EXC_PC_DBD; |
| if (ebreak_into_debug && !debug_mode_q) begin |
| csr_save_cause_o = 1'b1; |
| csr_save_id_o = 1'b1; |
| debug_csr_save_o = 1'b1; |
| debug_cause_o = DBG_CAUSE_EBREAK; |
| end |
| debug_mode_d = 1'b1; |
| ctrl_fsm_ns = DECODE; |
| end |
| FLUSH: begin |
| halt_if = 1'b1; |
| flush_id = 1'b1; |
| ctrl_fsm_ns = DECODE; |
| if ((exc_req_q || store_err_q) || load_err_q) begin |
| pc_set_o = 1'b1; |
| pc_set_spec_o = 1'b1; |
| pc_mux_o = PC_EXC; |
| exc_pc_mux_o = (debug_mode_q ? EXC_PC_DBG_EXC : EXC_PC_EXC); |
| if (WritebackStage) begin : g_writeback_mepc_save |
| csr_save_id_o = ~(store_err_q | load_err_q); |
| csr_save_wb_o = store_err_q | load_err_q; |
| end |
| else begin : g_no_writeback_mepc_save |
| csr_save_id_o = 1'b0; |
| end |
| csr_save_cause_o = 1'b1; |
| case (1'b1) |
| instr_fetch_err_prio: begin |
| exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT; |
| csr_mtval_o = (instr_fetch_err_plus2_i ? pc_id_i + 32'd2 : pc_id_i); |
| end |
| illegal_insn_prio: begin |
| exc_cause_o = EXC_CAUSE_ILLEGAL_INSN; |
| csr_mtval_o = (instr_is_compressed_i ? {16'b0000000000000000, instr_compressed_i} : instr_i); |
| end |
| ecall_insn_prio: exc_cause_o = (priv_mode_i == PRIV_LVL_M ? EXC_CAUSE_ECALL_MMODE : EXC_CAUSE_ECALL_UMODE); |
| ebrk_insn_prio: |
| if (debug_mode_q | ebreak_into_debug) begin |
| pc_set_o = 1'b0; |
| pc_set_spec_o = 1'b0; |
| csr_save_id_o = 1'b0; |
| csr_save_cause_o = 1'b0; |
| ctrl_fsm_ns = DBG_TAKEN_ID; |
| flush_id = 1'b0; |
| end |
| else |
| exc_cause_o = EXC_CAUSE_BREAKPOINT; |
| store_err_prio: begin |
| exc_cause_o = EXC_CAUSE_STORE_ACCESS_FAULT; |
| csr_mtval_o = lsu_addr_last_i; |
| end |
| load_err_prio: begin |
| exc_cause_o = EXC_CAUSE_LOAD_ACCESS_FAULT; |
| csr_mtval_o = lsu_addr_last_i; |
| end |
| default: |
| ; |
| endcase |
| end |
| else if (mret_insn) begin |
| pc_mux_o = PC_ERET; |
| pc_set_o = 1'b1; |
| pc_set_spec_o = 1'b1; |
| csr_restore_mret_id_o = 1'b1; |
| if (nmi_mode_q) |
| nmi_mode_d = 1'b0; |
| end |
| else if (dret_insn) begin |
| pc_mux_o = PC_DRET; |
| pc_set_o = 1'b1; |
| pc_set_spec_o = 1'b1; |
| debug_mode_d = 1'b0; |
| csr_restore_dret_id_o = 1'b1; |
| end |
| else if (wfi_insn) |
| ctrl_fsm_ns = WAIT_SLEEP; |
| else if (csr_pipe_flush && handle_irq) |
| ctrl_fsm_ns = IRQ_TAKEN; |
| if (enter_debug_mode && !(ebrk_insn_prio && ebreak_into_debug)) |
| ctrl_fsm_ns = DBG_TAKEN_IF; |
| end |
| default: begin |
| instr_req_o = 1'b0; |
| ctrl_fsm_ns = RESET; |
| end |
| endcase |
| end |
| assign flush_id_o = flush_id; |
| assign debug_mode_o = debug_mode_q; |
| assign nmi_mode_o = nmi_mode_q; |
| assign stall = stall_id_i | stall_wb_i; |
| assign id_in_ready_o = (~stall & ~halt_if) & ~retain_id; |
| assign instr_valid_clear_o = ~(stall | retain_id) | flush_id; |
| always @(posedge clk_i or negedge rst_ni) begin : update_regs |
| if (!rst_ni) begin |
| ctrl_fsm_cs <= RESET; |
| nmi_mode_q <= 1'b0; |
| debug_mode_q <= 1'b0; |
| load_err_q <= 1'b0; |
| store_err_q <= 1'b0; |
| exc_req_q <= 1'b0; |
| illegal_insn_q <= 1'b0; |
| end |
| else begin |
| ctrl_fsm_cs <= ctrl_fsm_ns; |
| nmi_mode_q <= nmi_mode_d; |
| debug_mode_q <= debug_mode_d; |
| load_err_q <= load_err_d; |
| store_err_q <= store_err_d; |
| exc_req_q <= exc_req_d; |
| illegal_insn_q <= illegal_insn_d; |
| end |
| end |
| endmodule |
