FULL RUN LOG:
 Uncompressing the gds files
Step 0 done without fatal errors.
 Executing Step 1 of 4: Checking License files.
{{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
 No third party libraries found.
Step 1 done without fatal errors.
{{SPDX COMPLIANCE WARNING}} Found 129 non-compliant files with the SPDX Standard. Check full log for more information
SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/scripts/create-caravel-diagram.py', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/picorv32.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/simpleuart.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project_wrapper.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/mgmt_soc.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/spimemio.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/fabric_netlists.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/fpga_top.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/top_autocheck_top_tb.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/InstancesMap.txt', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/tie_array.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/fpga_core.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/top_formal_random_top_tb.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/define_simulation.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/top_top_formal_verification.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/fpga_defines.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/top_include_netlists.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/cbx_1__2_.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/cby_1__1_.v', '/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/sb_1__2_.v']
 Executing Step 2 of 4: Checking YAML description.
 YAML file valid!
Step 2 done without fatal errors.
 Executing Step 3 of 4: Executing Fuzzy Consistency Checks.
b'Going into /mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl'
b'Removing manifest'
b'Fetching manifest'
b'Running sha1sum checks'
b'Going into /mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/maglef'
b'Removing manifest'
b'Fetching manifest'
b'Running sha1sum checks'
b'Going into /mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/mag'
b'Removing manifest'
b'Fetching manifest'
b'Running sha1sum checks'
 Manifest Check Failed. Make sure you mounted the docker or you're using the docker version that has sha1sum installed. Also, The manifest file might be deleted from caravel master at the moment.

 Documentation Checks Passed.
 Makefile Checks Passed.
 Fuzzy Consistency Checks Passed!
Step 3 done without fatal errors.
 Executing Step 4 of 4: Checking DRC Violations.
 Running DRC Checks...
 DRC Checks on MAG Passed!
Step 4 done without fatal errors.
 All Checks PASSED!