FULL RUN LOG:
SPDX NON-COMPLIANT FILES
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/scripts/create-caravel-diagram.py
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/picorv32.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/simpleuart.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project_wrapper.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/mgmt_soc.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/spimemio.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/fabric_netlists.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/fpga_top.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/top_autocheck_top_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/InstancesMap.txt
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/tie_array.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/fpga_core.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/top_formal_random_top_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/define_simulation.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/top_top_formal_verification.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/fpga_defines.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/top_include_netlists.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/cbx_1__2_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/cby_1__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/sb_1__2_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/sb_2__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/sb_1__0_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/sb_0__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/cbx_1__0_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/cby_2__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/sb_2__2_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/sb_0__0_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/sb_2__0_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/sb_0__2_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/sb_1__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/cbx_1__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/routing/cby_0__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/lb/grid_clb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/lb/logical_tile_io_mode_physical__iopad.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/lb/logical_tile_clb_mode_default__fle.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/lb/logical_tile_io_mode_io_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/lb/logical_tile_clb_mode_clb_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/sub_module/inv_buf_passgate.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/sub_module/digital_io_hd.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/sub_module/luts.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/sub_module/muxes.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/sub_module/wires.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/sub_module/local_encoder.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/sub_module/arch_encoder.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/sub_module/user_project_wrapper.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/rtl/user_project/SRC/sub_module/memories.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/tbuart.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/spiflash.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/sections.lds
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/start.s
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/user_proj_example/and2/and2.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/caravel/tbuart.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/caravel/spiflash.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/caravel/sections.lds
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/caravel/start.s
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/caravel/mgmt_soc/uart/uart_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/caravel/mgmt_soc/timer/timer_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/caravel/mgmt_soc/storage/storage_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/caravel/mgmt_soc/perf/perf_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/caravel/mgmt_soc/timer2/timer2_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/caravel/mgmt_soc/gpio/gpio_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/caravel/mgmt_soc/mem/mem_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_proj_example.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/caravel.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/mgmt_protect_hv.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/mgmt_core.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/mgmt_protect.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/mprj_logic_high.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project_wrapper.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/gpio_control_block.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/mprj2_logic_high.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/chip_io.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/cbx_1__2_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/cby_1__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/sb_1__2_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/sb_2__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/tie_array.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/grid_clb.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/fpga_core.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/sb_1__0_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/sb_0__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/cbx_1__0_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/cby_2__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/sb_2__2_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/user_project_wrapper.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/sb_0__0_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/sb_2__0_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/sb_0__2_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/sb_1__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/cbx_1__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/verilog/gl/user_project/gl/cby_0__1_.v
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/caravel.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/mgmt_protect_hv.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/simple_por.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/DFFRAM.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/user_proj_example.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/mprj2_logic_high.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/chip_io.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/gpio_control_block.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/mprj_logic_high.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/mgmt_protect.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/user_project_wrapper.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/storage.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/digital_pll.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/mgmt_core.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/spi/lvs/user_id_programming.spice
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/signoff/waivers
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/signoff/versions
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/signoff/make_final
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/openlane/chip_dimensions.txt
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/openlane/mgmt_protect/pdn.tcl
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/doc/manfucturability_report.rpt
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/doc/caravel_datasheet.ps
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/docs/manfucturability_report.rpt
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/docs/caravel_datasheet.ps
/mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/mag/clamp_list.txt