
reading lef ...

units:       1000
#layers:     13
#macros:     437
#vias:       25
#viarulegen: 25

reading def ...

design:      user_proj_example
die area:    ( 0 0 ) ( 250000 250000 )
trackPts:    12
defvias:     4
#components: 5304
#terminals:  614
#snets:      2
#nets:       1030

reading guide ...

#guides:     5912
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: via2_FR
  Layer via3
    default via: M3M4_PR_M
  Layer via4
    default via: via4_FR
Writing reference output def...

libcell analysis ...

instance analysis ...
#unique instances = 58

init region query ...
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 45579
mcon shape region query size = 86876
met1 shape region query size = 12526
via shape region query size = 504
met2 shape region query size = 620
via2 shape region query size = 504
met3 shape region query size = 496
via3 shape region query size = 504
met4 shape region query size = 134
via4 shape region query size = 5
met5 shape region query size = 10


start pin access
  complete 100 pins
  complete 138 pins
  complete 52 unique inst patterns
  complete 683 groups
Expt1 runtime (pin-level access point gen): 0.413658
Expt2 runtime (design-level access pattern gen): 0.0499152
#scanned instances     = 5304
#unique  instances     = 58
#stdCellGenAp          = 926
#stdCellValidPlanarAp  = 0
#stdCellValidViaAp     = 648
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 1926
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0

complete pin access
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 24.17 (MB), peak = 25.46 (MB)

post process guides ...
GCELLGRID X -1 DO 36 STEP 6900 ;
GCELLGRID Y -1 DO 36 STEP 6900 ;
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

building cmap ... 

init guide query ...
  complete FR_MASTERSLICE (guide)
  complete FR_VIA (guide)
  complete li1 (guide)
  complete mcon (guide)
  complete met1 (guide)
  complete via (guide)
  complete met2 (guide)
  complete via2 (guide)
  complete met3 (guide)
  complete via3 (guide)
  complete met4 (guide)
  complete via4 (guide)
  complete met5 (guide)

FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 1816
mcon guide region query size = 0
met1 guide region query size = 1872
via guide region query size = 0
met2 guide region query size = 1301
via2 guide region query size = 0
met3 guide region query size = 198
via3 guide region query size = 0
met4 guide region query size = 6
via4 guide region query size = 0
met5 guide region query size = 2

init gr pin query ...


start track assignment
Done with 3123 vertical wires in 1 frboxes and 2072 horizontal wires in 1 frboxes.
Done with 369 vertical wires in 1 frboxes and 752 horizontal wires in 1 frboxes.

complete track assignment
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 43.65 (MB), peak = 62.32 (MB)

post processing ...

start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 43.66 (MB), peak = 62.32 (MB)

start detail routing ...
start 0th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 78.76 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 83.51 (MB)
    completing 30% with 638 violations
    elapsed time = 00:00:01, memory = 66.14 (MB)
    completing 40% with 638 violations
    elapsed time = 00:00:01, memory = 76.42 (MB)
    completing 50% with 638 violations
    elapsed time = 00:00:04, memory = 78.45 (MB)
    completing 60% with 933 violations
    elapsed time = 00:00:05, memory = 78.83 (MB)
    completing 70% with 933 violations
    elapsed time = 00:00:05, memory = 83.47 (MB)
    completing 80% with 1036 violations
    elapsed time = 00:00:05, memory = 78.42 (MB)
    completing 90% with 1036 violations
    elapsed time = 00:00:05, memory = 77.14 (MB)
    completing 100% with 834 violations
    elapsed time = 00:00:08, memory = 52.78 (MB)
  number of violations = 946
cpu time = 00:00:13, elapsed time = 00:00:08, memory = 395.15 (MB), peak = 395.36 (MB)
total wire length = 53605 um
total wire length on LAYER li1 = 6 um
total wire length on LAYER met1 = 23727 um
total wire length on LAYER met2 = 24596 um
total wire length on LAYER met3 = 4731 um
total wire length on LAYER met4 = 337 um
total wire length on LAYER met5 = 206 um
total number of vias = 5146
up-via summary (total 5146):

-----------------------
 FR_MASTERSLICE       0
            li1    1938
           met1    2851
           met2     345
           met3       8
           met4       4
-----------------------
                   5146


start 1st optimization iteration ...
    completing 10% with 946 violations
    elapsed time = 00:00:00, memory = 424.46 (MB)
    completing 20% with 946 violations
    elapsed time = 00:00:00, memory = 439.52 (MB)
    completing 30% with 903 violations
    elapsed time = 00:00:01, memory = 410.78 (MB)
    completing 40% with 903 violations
    elapsed time = 00:00:01, memory = 425.39 (MB)
    completing 50% with 903 violations
    elapsed time = 00:00:04, memory = 422.88 (MB)
    completing 60% with 736 violations
    elapsed time = 00:00:04, memory = 427.80 (MB)
    completing 70% with 736 violations
    elapsed time = 00:00:04, memory = 434.77 (MB)
    completing 80% with 636 violations
    elapsed time = 00:00:05, memory = 417.69 (MB)
    completing 90% with 636 violations
    elapsed time = 00:00:06, memory = 435.75 (MB)
    completing 100% with 416 violations
    elapsed time = 00:00:08, memory = 395.29 (MB)
  number of violations = 416
cpu time = 00:00:11, elapsed time = 00:00:08, memory = 395.29 (MB), peak = 446.32 (MB)
total wire length = 53247 um
total wire length on LAYER li1 = 15 um
total wire length on LAYER met1 = 23779 um
total wire length on LAYER met2 = 24491 um
total wire length on LAYER met3 = 4416 um
total wire length on LAYER met4 = 337 um
total wire length on LAYER met5 = 206 um
total number of vias = 5108
up-via summary (total 5108):

-----------------------
 FR_MASTERSLICE       0
            li1    1956
           met1    2810
           met2     330
           met3       8
           met4       4
-----------------------
                   5108


start 2nd optimization iteration ...
    completing 10% with 416 violations
    elapsed time = 00:00:00, memory = 397.00 (MB)
    completing 20% with 416 violations
    elapsed time = 00:00:01, memory = 448.63 (MB)
    completing 30% with 434 violations
    elapsed time = 00:00:01, memory = 398.70 (MB)
    completing 40% with 434 violations
    elapsed time = 00:00:02, memory = 427.91 (MB)
    completing 50% with 434 violations
    elapsed time = 00:00:02, memory = 434.17 (MB)
    completing 60% with 402 violations
    elapsed time = 00:00:02, memory = 423.52 (MB)
    completing 70% with 402 violations
    elapsed time = 00:00:02, memory = 437.07 (MB)
    completing 80% with 394 violations
    elapsed time = 00:00:05, memory = 423.29 (MB)
    completing 90% with 394 violations
    elapsed time = 00:00:05, memory = 425.25 (MB)
    completing 100% with 384 violations
    elapsed time = 00:00:07, memory = 395.36 (MB)
  number of violations = 384
cpu time = 00:00:11, elapsed time = 00:00:07, memory = 395.36 (MB), peak = 448.82 (MB)
total wire length = 53180 um
total wire length on LAYER li1 = 8 um
total wire length on LAYER met1 = 23658 um
total wire length on LAYER met2 = 24417 um
total wire length on LAYER met3 = 4529 um
total wire length on LAYER met4 = 354 um
total wire length on LAYER met5 = 211 um
total number of vias = 5049
up-via summary (total 5049):

-----------------------
 FR_MASTERSLICE       0
            li1    1942
           met1    2762
           met2     331
           met3      10
           met4       4
-----------------------
                   5049


start 3rd optimization iteration ...
    completing 10% with 384 violations
    elapsed time = 00:00:00, memory = 437.58 (MB)
    completing 20% with 384 violations
    elapsed time = 00:00:00, memory = 437.69 (MB)
    completing 30% with 319 violations
    elapsed time = 00:00:00, memory = 408.29 (MB)
    completing 40% with 319 violations
    elapsed time = 00:00:00, memory = 436.82 (MB)
    completing 50% with 319 violations
    elapsed time = 00:00:02, memory = 434.88 (MB)
    completing 60% with 178 violations
    elapsed time = 00:00:02, memory = 433.02 (MB)
    completing 70% with 178 violations
    elapsed time = 00:00:02, memory = 433.06 (MB)
    completing 80% with 131 violations
    elapsed time = 00:00:02, memory = 410.25 (MB)
    completing 90% with 131 violations
    elapsed time = 00:00:03, memory = 426.19 (MB)
    completing 100% with 20 violations
    elapsed time = 00:00:03, memory = 408.25 (MB)
  number of violations = 20
cpu time = 00:00:07, elapsed time = 00:00:03, memory = 408.25 (MB), peak = 449.71 (MB)
total wire length = 53172 um
total wire length on LAYER li1 = 9 um
total wire length on LAYER met1 = 22605 um
total wire length on LAYER met2 = 24288 um
total wire length on LAYER met3 = 5543 um
total wire length on LAYER met4 = 514 um
total wire length on LAYER met5 = 211 um
total number of vias = 5198
up-via summary (total 5198):

-----------------------
 FR_MASTERSLICE       0
            li1    1940
           met1    2787
           met2     442
           met3      25
           met4       4
-----------------------
                   5198


start 4th optimization iteration ...
    completing 10% with 20 violations
    elapsed time = 00:00:00, memory = 423.22 (MB)
    completing 20% with 20 violations
    elapsed time = 00:00:00, memory = 432.89 (MB)
    completing 30% with 11 violations
    elapsed time = 00:00:00, memory = 414.02 (MB)
    completing 40% with 11 violations
    elapsed time = 00:00:00, memory = 415.63 (MB)
    completing 50% with 11 violations
    elapsed time = 00:00:00, memory = 415.63 (MB)
    completing 60% with 11 violations
    elapsed time = 00:00:00, memory = 428.11 (MB)
    completing 70% with 11 violations
    elapsed time = 00:00:00, memory = 435.46 (MB)
    completing 80% with 2 violations
    elapsed time = 00:00:00, memory = 409.61 (MB)
    completing 90% with 2 violations
    elapsed time = 00:00:00, memory = 401.45 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 407.81 (MB)
  number of violations = 0
cpu time = 00:00:02, elapsed time = 00:00:00, memory = 407.81 (MB), peak = 449.71 (MB)
total wire length = 53176 um
total wire length on LAYER li1 = 9 um
total wire length on LAYER met1 = 22610 um
total wire length on LAYER met2 = 24286 um
total wire length on LAYER met3 = 5546 um
total wire length on LAYER met4 = 512 um
total wire length on LAYER met5 = 211 um
total number of vias = 5196
up-via summary (total 5196):

-----------------------
 FR_MASTERSLICE       0
            li1    1940
           met1    2787
           met2     442
           met3      23
           met4       4
-----------------------
                   5196


start 17th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 398.82 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 412.48 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 405.89 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 414.74 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 408.57 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 405.28 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 407.02 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 411.05 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 406.83 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 400.49 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 400.49 (MB), peak = 449.71 (MB)
total wire length = 53176 um
total wire length on LAYER li1 = 9 um
total wire length on LAYER met1 = 22610 um
total wire length on LAYER met2 = 24286 um
total wire length on LAYER met3 = 5546 um
total wire length on LAYER met4 = 512 um
total wire length on LAYER met5 = 211 um
total number of vias = 5196
up-via summary (total 5196):

-----------------------
 FR_MASTERSLICE       0
            li1    1940
           met1    2787
           met2     442
           met3      23
           met4       4
-----------------------
                   5196


start 25th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 401.23 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 405.59 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 397.74 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 400.95 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 397.16 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 400.44 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 402.20 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 400.70 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 402.91 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 399.45 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 399.45 (MB), peak = 449.71 (MB)
total wire length = 53176 um
total wire length on LAYER li1 = 9 um
total wire length on LAYER met1 = 22610 um
total wire length on LAYER met2 = 24286 um
total wire length on LAYER met3 = 5546 um
total wire length on LAYER met4 = 512 um
total wire length on LAYER met5 = 211 um
total number of vias = 5196
up-via summary (total 5196):

-----------------------
 FR_MASTERSLICE       0
            li1    1940
           met1    2787
           met2     442
           met3      23
           met4       4
-----------------------
                   5196


start 33rd optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 397.41 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 397.75 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 396.94 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 399.52 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 398.50 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 398.57 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 398.39 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 398.72 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 397.37 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 398.28 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 398.28 (MB), peak = 449.71 (MB)
total wire length = 53176 um
total wire length on LAYER li1 = 9 um
total wire length on LAYER met1 = 22610 um
total wire length on LAYER met2 = 24286 um
total wire length on LAYER met3 = 5546 um
total wire length on LAYER met4 = 512 um
total wire length on LAYER met5 = 211 um
total number of vias = 5196
up-via summary (total 5196):

-----------------------
 FR_MASTERSLICE       0
            li1    1940
           met1    2787
           met2     442
           met3      23
           met4       4
-----------------------
                   5196


start 41st optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 398.15 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 399.02 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 396.50 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 397.65 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 398.74 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 398.19 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 398.29 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 397.67 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 398.46 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 398.81 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 398.81 (MB), peak = 449.71 (MB)
total wire length = 53176 um
total wire length on LAYER li1 = 9 um
total wire length on LAYER met1 = 22610 um
total wire length on LAYER met2 = 24286 um
total wire length on LAYER met3 = 5546 um
total wire length on LAYER met4 = 512 um
total wire length on LAYER met5 = 211 um
total number of vias = 5196
up-via summary (total 5196):

-----------------------
 FR_MASTERSLICE       0
            li1    1940
           met1    2787
           met2     442
           met3      23
           met4       4
-----------------------
                   5196


start 49th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 398.66 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 399.66 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 397.77 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 398.62 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 398.40 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 398.84 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 397.42 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 398.82 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 399.34 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 397.91 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 397.91 (MB), peak = 449.71 (MB)
total wire length = 53176 um
total wire length on LAYER li1 = 9 um
total wire length on LAYER met1 = 22610 um
total wire length on LAYER met2 = 24286 um
total wire length on LAYER met3 = 5546 um
total wire length on LAYER met4 = 512 um
total wire length on LAYER met5 = 211 um
total number of vias = 5196
up-via summary (total 5196):

-----------------------
 FR_MASTERSLICE       0
            li1    1940
           met1    2787
           met2     442
           met3      23
           met4       4
-----------------------
                   5196


start 57th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 397.28 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 397.49 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 396.94 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 399.54 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 398.65 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 397.37 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 398.39 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 398.73 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 397.37 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 398.43 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 398.43 (MB), peak = 449.71 (MB)
total wire length = 53176 um
total wire length on LAYER li1 = 9 um
total wire length on LAYER met1 = 22610 um
total wire length on LAYER met2 = 24286 um
total wire length on LAYER met3 = 5546 um
total wire length on LAYER met4 = 512 um
total wire length on LAYER met5 = 211 um
total number of vias = 5196
up-via summary (total 5196):

-----------------------
 FR_MASTERSLICE       0
            li1    1940
           met1    2787
           met2     442
           met3      23
           met4       4
-----------------------
                   5196


complete detail routing
total wire length = 53176 um
total wire length on LAYER li1 = 9 um
total wire length on LAYER met1 = 22610 um
total wire length on LAYER met2 = 24286 um
total wire length on LAYER met3 = 5546 um
total wire length on LAYER met4 = 512 um
total wire length on LAYER met5 = 211 um
total number of vias = 5196
up-via summary (total 5196):

-----------------------
 FR_MASTERSLICE       0
            li1    1940
           met1    2787
           met2     442
           met3      23
           met4       4
-----------------------
                   5196

cpu time = 00:00:55, elapsed time = 00:00:33, memory = 398.43 (MB), peak = 449.71 (MB)

post processing ...

Runtime taken (hrt): 35.4092