Design Name: user_project_wrapper
Run Directory: /ef/openfpga/openlane/runs/user_project_wrapper/
----------------------------------------

Magic DRC Summary:
Source: /ef/openfpga/openlane/runs/user_project_wrapper//logs/magic/magic.drc
Total Magic DRC violations is 0
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LVS Summary:
Source: /ef/openfpga/openlane/runs/user_project_wrapper//results/lvs/user_project_wrapper.lvs_parsed.log
LVS reports no net, device, pin, or property mismatches.
Total errors = 0
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Antenna Summary:
Source: /ef/openfpga/openlane/runs/user_project_wrapper//reports/routing/antenna.rpt
Number of pins violated: 22
Number of nets violated: 13