Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 69 library cells
Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/simple_por/runs/simple_por/results/routing/simple_por.def
Notice 0: Design: simple_por
Notice 0:     Created 5 pins.
Notice 0:     Created 16 components and 70 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 5 nets and 5 connections.
Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/results/routing/simple_por.def
Top-level design name: simple_por
Found port VPWR of type SIGNAL
Found port VGND of type SIGNAL
Power net:  VPWR
Ground net: VGND
Modified power connections of 16 cells (Remaining: 0 ).