)]}'
{
  "commit": "5f928bc28babedb30482fd63efcbe3bb308c91c0",
  "tree": "47e88b95e88e905a6041bc7b286a1c0dde50956c",
  "parents": [
    "9ed16cc7b77ccf2c6ee9cb2604a3cef4eb862168"
  ],
  "author": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Thu Dec 10 00:38:25 2020 +0200"
  },
  "committer": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Thu Dec 10 00:38:25 2020 +0200"
  },
  "message": "Integrated fpga_top with caravel\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2c77d56a142ea4189a207d8f3ec12722963cc867",
      "old_mode": 33188,
      "old_path": "README.md",
      "new_id": "f63247495e36150ecce6234f7d597233b46f1cfd",
      "new_mode": 33188,
      "new_path": "README.md"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "6b42fa3c9a56f578bcd16bf4073d111d3995edeb",
      "new_mode": 33188,
      "new_path": "doc/images/Caravel-FPGA.png"
    },
    {
      "type": "modify",
      "old_id": "82807828394b7f980ebe27d1ff5d98c26e8d9d27",
      "old_mode": 33188,
      "old_path": "gds/caravel.gds.gz",
      "new_id": "6253fda89500260360272ced528685af8a567f05",
      "new_mode": 33188,
      "new_path": "gds/caravel.gds.gz"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "17a0dbcafa269a89e58bead5febf8dae242a21f6",
      "new_mode": 33188,
      "new_path": "gds/user_project_wrapper.gds"
    },
    {
      "type": "modify",
      "old_id": "f73d802188e2e00c8715e2a3b941ce44f94ce793",
      "old_mode": 33188,
      "old_path": "gds/user_project_wrapper.gds.gz",
      "new_id": "7f6fe683d7185a9ba57e81fe0ccdf7a2b4c27db8",
      "new_mode": 33188,
      "new_path": "gds/user_project_wrapper.gds.gz"
    }
  ]
}