)]}'
{
  "commit": "3f797359f8ef2addfbc0c958c6d380ff4eb33893",
  "tree": "42741e4fd503731c5af95bd870a2d3e5df770208",
  "parents": [
    "6c766a8fa8fde5afb13f4063bd22f5d72f712f64"
  ],
  "author": {
    "name": "agorararmard",
    "email": "aagouhar@efabless.com",
    "time": "Thu Dec 10 18:24:42 2020 +0200"
  },
  "committer": {
    "name": "agorararmard",
    "email": "aagouhar@efabless.com",
    "time": "Thu Dec 10 18:24:42 2020 +0200"
  },
  "message": "[LICENSE] Add SPDX headers to Makefiles\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "76a245e169d94d0e089fbe04a18915fefed32494",
      "old_mode": 33188,
      "old_path": "Makefile",
      "new_id": "18b66a481e353814d64d37ea13bc0edf27e43b27",
      "new_mode": 33188,
      "new_path": "Makefile"
    },
    {
      "type": "modify",
      "old_id": "44e94150c2c99613d578726b53cbf2eeaf2f3312",
      "old_mode": 33188,
      "old_path": "openlane/Makefile",
      "new_id": "1b637a7f01e61af77b810988c50eb12b9919ad84",
      "new_mode": 33188,
      "new_path": "openlane/Makefile"
    },
    {
      "type": "modify",
      "old_id": "acf62f9392d5c3711a791aca42cf16b2a60e61b5",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/Makefile",
      "new_id": "c7fd2d919fa4892bf6dccf028ed4711b89e1ed69",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/Makefile"
    },
    {
      "type": "modify",
      "old_id": "9eba5492c4d3b22f38bca019d800f902b0f96395",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/Makefile",
      "new_id": "5724f98765d79f162641792eb3780531abf2f383",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/Makefile"
    },
    {
      "type": "modify",
      "old_id": "4d47f981af2f6616480e1ec9932976b84e1d3dc6",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/hkspi/Makefile",
      "new_id": "1695a45569cc32a9ed6c0dd6bc8432067e1c1351",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/hkspi/Makefile"
    },
    {
      "type": "modify",
      "old_id": "d50e2616949453907e14fb7c596882643e310e5c",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/mem/Makefile",
      "new_id": "2be8c42c31faeccbedf0f1b248130277d4a0b751",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/mem/Makefile"
    },
    {
      "type": "modify",
      "old_id": "1f5ee62e650cd6adc915656ac21825255a2c7884",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile",
      "new_id": "64e99edfceb847015a8c73e5f01d162184d05943",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile"
    },
    {
      "type": "modify",
      "old_id": "4969c6ac964cf3e024d8c68f1d533cd525d3a0ea",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/pass_thru/Makefile",
      "new_id": "2fba75902580216d10ae7d9e444bb267078c1a59",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/pass_thru/Makefile"
    },
    {
      "type": "modify",
      "old_id": "c08b51ffe04cd52ca4eaa8d3325d1bbe08b09189",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/perf/Makefile",
      "new_id": "ed26dced6b59a0a3d1ebb46f83aa709a4586a8e1",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/perf/Makefile"
    },
    {
      "type": "modify",
      "old_id": "c60b5afb1856cc31e5f2c2876fc3be33cecc63c2",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/pll/Makefile",
      "new_id": "f1f19aafc76e6fc5d9209514c6fb935cf50a00ae",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/pll/Makefile"
    },
    {
      "type": "modify",
      "old_id": "dace1f74074d349247e6161d0ab9efbf3c4f5a81",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/storage/Makefile",
      "new_id": "11b0b049a2abd154ecbeb94445019cf2282a699c",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/storage/Makefile"
    },
    {
      "type": "modify",
      "old_id": "351c7409165a8f9b1f13d1356db62916bb40adce",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/sysctrl/Makefile",
      "new_id": "4816f03d5e833fcc005b172df88536504fbc2cb4",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/sysctrl/Makefile"
    },
    {
      "type": "modify",
      "old_id": "a62f01c001af8b94868e19fd185af23a1bf62d6c",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer/Makefile",
      "new_id": "d7b66b8092ecc39520fa8e3b7d2c6afc73c405e2",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer/Makefile"
    },
    {
      "type": "modify",
      "old_id": "e054fa89e831ba3dda852de1b154abe198305ccb",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer2/Makefile",
      "new_id": "0be97ef2557c1f1d5be20c6b79fada23b98e7e41",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer2/Makefile"
    },
    {
      "type": "modify",
      "old_id": "e421c20d3f1cb5e5492b9b1db280f8c64f90d7be",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/uart/Makefile",
      "new_id": "e4469478d493a8ff2d7b2a5224407f8245a26204",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/uart/Makefile"
    },
    {
      "type": "modify",
      "old_id": "6b5248cae8ebbe0a0ff60828bcbc751a5f62448a",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/Makefile",
      "new_id": "7e37e0268e65ce376163bb81f2a3d84f21198c3b",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/Makefile"
    },
    {
      "type": "modify",
      "old_id": "3ab627215551b9fd1de58f209f425ec97705d8d7",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/io_ports/Makefile",
      "new_id": "6b630a3fe947d0b186cd65c8945e814718b90084",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/io_ports/Makefile"
    },
    {
      "type": "modify",
      "old_id": "19fd4a114f25bc4adfe7171a26a844fc97ea9eac",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test1/Makefile",
      "new_id": "677a8d7d21ee48e420cdc329100645ef9f612cc7",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/la_test1/Makefile"
    },
    {
      "type": "modify",
      "old_id": "d9d9a0d88828e6a2917db01ecb6bd9ff7e2afa30",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test2/Makefile",
      "new_id": "22b99cb61f327e609afefa25c43368b5c7c6da84",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/la_test2/Makefile"
    },
    {
      "type": "modify",
      "old_id": "930e5b525133e222eb4bf00f5663766c51d0d295",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/Makefile",
      "new_id": "9684dfc0f4967e94833f94d8ec12493eab891d7e",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/Makefile"
    },
    {
      "type": "modify",
      "old_id": "d8d54e4771b5e95d2c8f6c7d5da4e65f2bb00f80",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/gpio_wb/Makefile",
      "new_id": "a42f609b79fa7fd01fb621de6b0f48eacb47ffb9",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/gpio_wb/Makefile"
    },
    {
      "type": "modify",
      "old_id": "e061e8d508dd8a57563b9fb559e2a1dd17ae62eb",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/intercon_wb/Makefile",
      "new_id": "294cf175d60c82a683430a9dff58313f998906d8",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/intercon_wb/Makefile"
    },
    {
      "type": "modify",
      "old_id": "216614fa8db22a28880ce48d448dacb336056352",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/la_wb/Makefile",
      "new_id": "1b76d6b81b74eb42bae7e86b9d999694a21e448d",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/la_wb/Makefile"
    },
    {
      "type": "modify",
      "old_id": "82b2235d10ea248dc43c866a1863a5fdd93f030e",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/mem_wb/Makefile",
      "new_id": "4ed37bf23684fd57983698bec20800da25052187",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/mem_wb/Makefile"
    },
    {
      "type": "modify",
      "old_id": "841be9ecfe2eb41803c3c59ab6862fc187f2912a",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/mprj_ctrl/Makefile",
      "new_id": "f35401809c296f001af4fb18a1b74279c2b9198d",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/mprj_ctrl/Makefile"
    },
    {
      "type": "modify",
      "old_id": "55b9235d550753ce096a120b1298cca39eb189c2",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/spi_sysctrl_wb/Makefile",
      "new_id": "8bf03c7d0f10d1cc40c306e80e9f81d55e4dac64",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/spi_sysctrl_wb/Makefile"
    },
    {
      "type": "modify",
      "old_id": "075241d50cb1071e4d586c5add2acf5ee5a6645f",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/spimemio_wb/Makefile",
      "new_id": "d145f0467dab5f67ae396b654759917337540a21",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/spimemio_wb/Makefile"
    },
    {
      "type": "modify",
      "old_id": "4ff890f6b3b67ce0bc40745e52415e62d71403fd",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/storage_wb/Makefile",
      "new_id": "d080bcfd7a2d3a2cca638a9f714c9344e2aaaf15",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/storage_wb/Makefile"
    },
    {
      "type": "modify",
      "old_id": "e1b0978052bbed8c203d671f83f2cda5d6903e75",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/sysctrl_wb/Makefile",
      "new_id": "89aa77bb32fc1f091c85898fd6b6242fb3a9321c",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/sysctrl_wb/Makefile"
    },
    {
      "type": "modify",
      "old_id": "a37bd82d3feac956b951a54a29d059e05b548b6a",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/uart_wb/Makefile",
      "new_id": "d1c587f4d03eb77f3a877a87966d0858be7fed9a",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/uart_wb/Makefile"
    }
  ]
}
