)]}'
{
  "commit": "d0586c081ac65f4eed9e1554bb8d7f7ca7f6b385",
  "tree": "91294fc6f25d631373c4d7828e38a664d0f75656",
  "parents": [
    "7b635bc150e2cf3d4f3b0a512eb30ce01a0934ae"
  ],
  "author": {
    "name": "Maximilian Barger",
    "email": "mbarger@internships.antmicro.com",
    "time": "Mon Nov 30 19:19:10 2020 +0100"
  },
  "committer": {
    "name": "Maximilian Barger",
    "email": "mbarger@internships.antmicro.com",
    "time": "Tue Jan 26 12:27:16 2021 +0100"
  },
  "message": "User project wrapper: use user_proj_aes\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "faaee02855d92be64b6c5974cefd30688412de8d",
      "old_mode": 33188,
      "old_path": "openlane/user_project_wrapper_empty/config.tcl",
      "new_id": "792b44577d3252ab5933cf6b7bdb0af954f8edb1",
      "new_mode": 33188,
      "new_path": "openlane/user_project_wrapper_empty/config.tcl"
    },
    {
      "type": "modify",
      "old_id": "47d92f4d6bb0cdbdca2175f28fa88f12fd574096",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "1dcf92ab09419fd6eee10388c325f588e06754d6",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}