)]}'
{
  "commit": "b9907d310285f2d4009534a768e8ce8590afeb7a",
  "tree": "ef869682a0b49eb5d080e5edc04e80de53ea3608",
  "parents": [
    "20e59be8293bc73bad7aa0c2cd80b41366d3f3dc"
  ],
  "author": {
    "name": "Maximilian Barger",
    "email": "mbarger@internships.antmicro.com",
    "time": "Thu Jan 28 14:22:02 2021 +0100"
  },
  "committer": {
    "name": "Maximilian Barger",
    "email": "mbarger@internships.antmicro.com",
    "time": "Thu Jan 28 14:22:02 2021 +0100"
  },
  "message": "user_proj_aes: Fix DRC errors\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "15a9ebbab75f992734171f771bfba3b1065873c6",
      "old_mode": 33188,
      "old_path": "openlane/user_proj_aes/config.tcl",
      "new_id": "f94efcce66206ff567aadd159168e3b16422d842",
      "new_mode": 33188,
      "new_path": "openlane/user_proj_aes/config.tcl"
    },
    {
      "type": "modify",
      "old_id": "a3c0dbca30c975b60f051edb893bd94f39e9ae16",
      "old_mode": 33188,
      "old_path": "openlane/user_project_wrapper/macro.cfg",
      "new_id": "7545c5214912465b946bfdf7ce3a4c2495d8bceb",
      "new_mode": 33188,
      "new_path": "openlane/user_project_wrapper/macro.cfg"
    }
  ]
}
