)]}'
{
  "commit": "b8bd47b1f3699d727888d74186498de7e46eb305",
  "tree": "526bd00c5dad36d02a461bfe6196b4c87fc5cd4e",
  "parents": [
    "d0586c081ac65f4eed9e1554bb8d7f7ca7f6b385"
  ],
  "author": {
    "name": "Maximilian Barger",
    "email": "mbarger@internships.antmicro.com",
    "time": "Wed Dec 02 17:18:25 2020 +0100"
  },
  "committer": {
    "name": "Maximilian Barger",
    "email": "mbarger@internships.antmicro.com",
    "time": "Tue Jan 26 12:27:17 2021 +0100"
  },
  "message": "aes_core: Latch e_done signal\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "35621099406950dc20690623b05e76cf5f0b29a2",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_aes/aes_core.v",
      "new_id": "4863c7367ac17c9481053951333ef6c29674b0f4",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_proj_aes/aes_core.v"
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}