diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index e60639f..7363773 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -25,13 +25,15 @@
 ## Source Verilog Files
 set ::env(VERILOG_FILES) "\
 	$script_dir/../../verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_project_wrapper.v"
+        $script_dir/../../verilog/rtl/user_project_wrapper.v"
+	#$script_dir/../../verilog/rtl/user_proj_aes/aes_core.v"
 
 ## Clock configurations
 set ::env(CLOCK_PORT) "user_clock2"
 set ::env(CLOCK_NET) "mprj.clk"
 
 set ::env(CLOCK_PERIOD) "10"
+set ::env(_SPACING) 1.7
 
 ## Internal Macros
 ### Macro Placement
@@ -40,13 +42,20 @@
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$script_dir/../../verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_proj_example.v"
+	$script_dir/../../third_party/aes_128/aes_cipher_top.v \
+	$script_dir/../../third_party/aes_128/aes_inv_cipher_top.v \
+	$script_dir/../../third_party/aes_128/aes_inv_sbox.v \
+	$script_dir/../../third_party/aes_128/aes_key_expand_128.v \
+	$script_dir/../../third_party/aes_128/aes_rcon.v \
+	$script_dir/../../third_party/aes_128/aes_sbox.v \
+	$script_dir/../../verilog/rtl/user_proj_aes/aes_core.v"
+	#$script_dir/../../verilog/rtl/user_proj_example.v"
 
 set ::env(EXTRA_LEFS) "\
-	$script_dir/../../lef/user_proj_example.lef"
+	$script_dir/../../lef/user_proj_aes.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$script_dir/../../gds/user_proj_example.gds"
+	$script_dir/../../gds/user_proj_aes.gds"
 
 
 # The following is because there are no std cells in the example wrapper project.
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index cab6c9d..7545c52 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1700 N
+mprj 100 100 N