diff --git a/verilog/rtl/user_proj_aes/aes_core.v b/verilog/rtl/user_proj_aes/aes_core.v
index 4863c73..0039442 100644
--- a/verilog/rtl/user_proj_aes/aes_core.v
+++ b/verilog/rtl/user_proj_aes/aes_core.v
@@ -1,7 +1,18 @@
+// Copyright 2020 Antmicro
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
 `default_nettype none
-/*
- *
- */
 
 module user_proj_aes #(
 	parameter BITS = 32