)]}'
{
  "commit": "20ce491e36aa46d630f87a8eed9de823f3355d2c",
  "tree": "8d2f2b83c7a19a95099bd1bcf41294c2ec3b3157",
  "parents": [
    "b65ade7f2d614c6c90e391c3aa86111ed85ba901"
  ],
  "author": {
    "name": "Maximilian Barger",
    "email": "mbarger@internships.antmicro.com",
    "time": "Tue Dec 08 10:43:04 2020 +0100"
  },
  "committer": {
    "name": "Maximilian Barger",
    "email": "mbarger@internships.antmicro.com",
    "time": "Tue Jan 26 12:27:17 2021 +0100"
  },
  "message": "User Project: Add testbench\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "49cd280c36bdf19bd4dba039bdb20e874cb5b139",
      "old_mode": 33188,
      "old_path": "verilog/dv/README.md",
      "new_id": "4152f512cdf159cae8b7ad115f56e6cd8b85e828",
      "new_mode": 33188,
      "new_path": "verilog/dv/README.md"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "5a55befb4aade2175ead88743e40ac14dd0b51c5",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_proj_aes_tests/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3993f10bbea32fda9e6638224d45cf7489f6e434",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_proj_aes_tests/aes_wb/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "77cfea1913683ed486ed30e1542c9a225c02dfee",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_proj_aes_tests/aes_wb/aes_wb_tb.v"
    }
  ]
}