)]}'
{
  "commit": "cdf0f36fe232a8223306f6b75877b75297bcd400",
  "tree": "1b57fdc8ceb6251d87104b654db33d1a5b00d645",
  "parents": [
    "383d74b86d82cb4c2dca906bf2d63bef09ec48f5"
  ],
  "author": {
    "name": "Anton Blanchard",
    "email": "anton@linux.ibm.com",
    "time": "Sat Dec 19 09:17:22 2020 +1100"
  },
  "committer": {
    "name": "Anton Blanchard",
    "email": "anton@linux.ibm.com",
    "time": "Mon Feb 01 05:00:13 2021 -0600"
  },
  "message": "Use DFFRAM behavioural when doing RTL simulation\n\nIn RTL simluation we are doing almost gate level simulation of the DFFRAM\nwhich is very slow. Use the behavioural.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3c9e5951246bc9860982591fe3e8fda335de6ec8",
      "old_mode": 33188,
      "old_path": "verilog/rtl/defines.v",
      "new_id": "2b1c95b999a7a0454d879753c66386f8c0d4d5bb",
      "new_mode": 33188,
      "new_path": "verilog/rtl/defines.v"
    }
  ]
}