diff --git a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
index f87f055..ea6c772 100644
--- a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
+++ b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
@@ -32,7 +32,7 @@
 
     reg [31:0] wb_dat_i;
     reg [31:0] wb_adr_i;
-    reg [15:0] gpio_in_pad;
+    reg gpio_in_pad;
 
     wire wb_ack_o;
     wire [31:0] wb_dat_o;
@@ -71,10 +71,10 @@
     wire [31:0] gpio_pu_adr  = uut.BASE_ADR | uut.GPIO_PU;
     wire [31:0] gpio_pd_adr  = uut.BASE_ADR | uut.GPIO_PD;
 
-    reg [15:0] gpio_data;
-    reg [15:0] gpio_pu; 
-    reg [15:0] gpio_pd; 
-    reg [15:0] gpio_oeb;  
+    reg gpio_data;
+    reg gpio_pu; 
+    reg gpio_pd; 
+    reg gpio_oeb;  
 
     initial begin
         // Reset Operation
@@ -84,53 +84,53 @@
         #2;
 
         // Write to gpio_data reg
-        gpio_in_pad = 16'h FFFF;
-        gpio_data = 16'h A000;
+        gpio_in_pad = 1'b1;
+        gpio_data = 1'b1;
         write(gpio_adr, gpio_data);
        
         #2;
         // Read from gpio_data reg
         read(gpio_adr);
-        if (wb_dat_o !== {gpio_data, gpio_in_pad}) begin
+        if (wb_dat_o !== {30'd0, gpio_data, gpio_in_pad}) begin
             $display("Monitor: Error reading from gpio reg");
             $finish;
         end
         
         #2;
         // Write to pull-up reg
-        gpio_pu = 16'h 000f;
+        gpio_pu = 1'b1;
         write(gpio_pu_adr, gpio_pu);
         
         #2;
         // Read from pull-up reg
         read(gpio_pu_adr);
-        if (wb_dat_o !== {16'd0, gpio_pu}) begin
+        if (wb_dat_o !== {31'd0, gpio_pu}) begin
             $display("Monitor: Error reading from gpio pull-up reg");
             $finish;
         end
 
         #2;
         // Write to pull-down reg
-        gpio_pd = 16'h 00f0;
+        gpio_pd = 1'b1;
         write(gpio_pd_adr, gpio_pd);
         
         #2;
         // Read from pull-down reg
         read(gpio_pd_adr);
-        if (wb_dat_o !== {16'd0, gpio_pd}) begin
+        if (wb_dat_o !== {31'd0, gpio_pd}) begin
             $display("Monitor: Error reading from gpio pull-down reg");
             $finish;
         end
 
         #2;
         // Write to gpio enable reg
-        gpio_oeb = 16'h 00ff;
+        gpio_oeb = 1'b1;
         write(gpio_oeb_adr, gpio_oeb);
         
         #2;
         // Read from gpio enable reg
         read(gpio_oeb_adr);
-        if (wb_dat_o !== {16'd0, gpio_oeb}) begin
+        if (wb_dat_o !== {31'd0, gpio_oeb}) begin
             $display("Monitor: Error reading from gpio output enable reg");
             $finish;
         end
diff --git a/verilog/dv/wb_utests/la_wb/la_wb_tb.v b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
index 92cc551..6839fdc 100644
--- a/verilog/dv/wb_utests/la_wb/la_wb_tb.v
+++ b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
@@ -89,48 +89,11 @@
         wb_rst_i = 0; 
         #2;
 
-        // Write to la data registers
-        la_data_0 = $urandom_range(0, 2**32);
-        la_data_1 = $urandom_range(0, 2**32);
-        la_data_2 = $urandom_range(0, 2**32);
-        la_data_3 = $urandom_range(0, 2**32);
-
-        write(la_data_adr_0, la_data_0);
-        write(la_data_adr_1, la_data_1);
-        write(la_data_adr_2, la_data_2);
-        write(la_data_adr_3, la_data_3);
-
-        #2;
-        // Read from la data registers
-        read(la_data_adr_0);
-        if (wb_dat_o !== la_data_0) begin
-            $display("Monitor: Error reading from la data_0 reg");
-            $finish;
-        end
-        
-        read(la_data_adr_1);
-        if (wb_dat_o !== la_data_1) begin
-            $display("Monitor: Error reading from la data_0 reg");
-            $finish;
-        end
-        
-        read(la_data_adr_2);
-        if (wb_dat_o !== la_data_1) begin
-            $display("Monitor: Error reading from la data_0 reg");
-            $finish;
-        end
-
-        read(la_data_adr_3);
-        if (wb_dat_o !== la_data_3) begin
-            $display("Monitor: Error reading from la data_0 reg");
-            $finish;
-        end
-
         // Write to la emable registers
-        la_ena_0 = $urandom_range(0, 2**32);
-        la_ena_1 = $urandom_range(0, 2**32);
-        la_ena_2 = $urandom_range(0, 2**32);
-        la_ena_3 = $urandom_range(0, 2**32);
+        la_ena_0 = 32'h0000_0000;
+        la_ena_1 = 32'h0000_0000;
+        la_ena_2 = 32'h0000_0000;
+        la_ena_3 = 32'h0000_0000;
 
         write(la_ena_adr_0, la_ena_0);
         write(la_ena_adr_1, la_ena_1);
@@ -141,27 +104,69 @@
         // Read from la data registers
         read(la_ena_adr_0);
         if (wb_dat_o !== la_ena_0) begin
-            $display("Monitor: Error reading from la data_0 reg");
+            $display("Monitor: Error reading from la_ena_0 reg");
             $finish;
         end
         
         read(la_ena_adr_1);
         if (wb_dat_o !== la_ena_1) begin
-            $display("Monitor: Error reading from la data_0 reg");
+            $display("Monitor: Error reading from la_ena_1 reg");
             $finish;
         end
         
         read(la_ena_adr_2);
         if (wb_dat_o !== la_ena_1) begin
-            $display("Monitor: Error reading from la data_0 reg");
+            $display("Monitor: Error reading from la_ena_2 reg");
             $finish;
         end
 
         read(la_ena_adr_3);
         if (wb_dat_o !== la_ena_3) begin
+            $display("Monitor: Error reading from la_ena_3 reg");
+            $finish;
+        end
+
+        // Write to la data registers
+        la_data_0 = $urandom_range(0, 2**30);
+        la_data_1 = $urandom_range(0, 2**30);
+        la_data_2 = $urandom_range(0, 2**30);
+        la_data_3 = $urandom_range(0, 2**30);
+
+        write(la_data_adr_0, la_data_0);
+        write(la_data_adr_1, la_data_1);
+        write(la_data_adr_2, la_data_2);
+        write(la_data_adr_3, la_data_3);
+
+        // #2;
+        // Read from la data registers
+        read(la_data_adr_0);
+        $display("%0b", wb_dat_o);
+        $display("%0b", la_data_0);
+
+        if (wb_dat_o !== la_data_0) begin
             $display("Monitor: Error reading from la data_0 reg");
             $finish;
         end
+        
+        read(la_data_adr_1);
+        if (wb_dat_o !== la_data_1) begin
+            $display("Monitor: Error reading from la data_1 reg");
+            $finish;
+        end
+        
+        read(la_data_adr_2);
+        $display("%0b", wb_dat_o);
+        $display("%0b", la_data_0);
+        if (wb_dat_o !== la_data_2) begin
+            $display("Monitor: Error reading from la data_2 reg");
+            $finish;
+        end
+
+        read(la_data_adr_3);
+        if (wb_dat_o !== la_data_3) begin
+            $display("Monitor: Error reading from la data_3 reg");
+            $finish;
+        end
         #6;
         $display("Monitor: Test LA Wishbone Success!");
         $display("Monitor: Test LA Wishbone Passed!");
diff --git a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
index 03c13a8..4784397 100644
--- a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
+++ b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
@@ -18,9 +18,15 @@
 
 `timescale 1 ns / 1 ps
 
-`define USE_OPENRAM
+`define FUNCTIONAL
+`define UNIT_DELAY #1
 
-`include "sram_1rw1r_32_8192_8_sky130.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+
+`include "defines.v"
+`include "DFFRAMBB.v"
+`include "DFFRAM.v"
 `include "mem_wb.v"
 
 module mem_wb_tb;
diff --git a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
index 6e5fd14..77140c7 100644
--- a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
+++ b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
@@ -62,11 +62,9 @@
     integer i;
     
     // System Control Default Register Addresses 
-    wire [31:0] clk1_out_adr   = uut.BASE_ADR | uut.CLK1_OUT;  
-    wire [31:0] clk2_out_adr   = uut.BASE_ADR | uut.CLK2_OUT;  
+    wire [31:0] clk_out_adr  = uut.BASE_ADR | uut.CLK_OUT;  
     wire [31:0] trap_out_adr  = uut.BASE_ADR | uut.TRAP_OUT;
-    wire [31:0] irq7_src_adr  = uut.BASE_ADR | uut.IRQ7_SRC;
-    wire [31:0] irq8_src_adr  = uut.BASE_ADR | uut.IRQ8_SRC;
+    wire [31:0] irq_src_adr  = uut.BASE_ADR | uut.IRQ_SRC;
 
     reg clk1_output_dest;
     reg clk2_output_dest;
@@ -88,42 +86,28 @@
         irq_8_inputsrc    = 1'b1;
 
         // Write to System Control Registers
-        write(clk1_out_adr, clk1_output_dest);
-        write(clk2_out_adr, clk2_output_dest);
+        write(clk_out_adr, clk1_output_dest);
         write(trap_out_adr, trap_output_dest);
-        write(irq7_src_adr, irq_7_inputsrc);
-        write(irq8_src_adr, irq_8_inputsrc);
+        write(irq_src_adr,  irq_7_inputsrc);
         #2;
-        read(clk1_out_adr);
+        read(clk_out_adr);
         if (wb_dat_o !== clk1_output_dest) begin
             $display("Error reading CLK1 output destination register.");
             $finish;
         end
 
-        read(clk2_out_adr);
-        if (wb_dat_o !== clk2_output_dest) begin
-            $display("Error reading CLK2 output destination register.");
-            $finish;
-        end
-
         read(trap_out_adr);
         if (wb_dat_o !== trap_output_dest) begin
             $display("Error reading trap output destination register.");
             $finish;
         end
 
-        read(irq7_src_adr);
+        read(irq_src_adr);
         if (wb_dat_o !== irq_7_inputsrc) begin
             $display("Error reading IRQ7 input source register.");
             $finish;
         end
 
-        read(irq8_src_adr);
-        if (wb_dat_o !== irq_8_inputsrc) begin
-            $display("Error reading IRQ8 input source register.");
-            $finish;
-        end
-
         $display("Success!");
         $display ("Monitor: Test System Control Passed!");
         $finish;