)]}'
{
  "commit": "5186c68d29401283325c14e7d6e8846cb5bea57a",
  "tree": "2fc0e6ffcbfb3371d74e6642e5b00acacdf0d15b",
  "parents": [
    "35fdac0b9af8a0c018369f888eb932bbb7ca5a04"
  ],
  "author": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Tue Jan 05 21:58:19 2021 +0200"
  },
  "committer": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Tue Jan 05 21:58:19 2021 +0200"
  },
  "message": "Specify root module in mem_wb Makefile\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f7dcab321bd6579daece3348e5b28de22326324d",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/mem_wb/Makefile",
      "new_id": "b018559719c8e3cf3ed173fabb66b0b88603df1f",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/mem_wb/Makefile"
    }
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}