)]}'
{
  "commit": "4078e1ea8049ae5ca6a17c35c60e11f89a78c3f5",
  "tree": "2f2723c785cf9ee727b0ab3ba05d56ead3e441f6",
  "parents": [
    "b7e1861538052839e5b9d01a8a546e3e489ed44f"
  ],
  "author": {
    "name": "agorararmard",
    "email": "aagouhar@efabless.com",
    "time": "Tue Jan 05 22:56:53 2021 +0200"
  },
  "committer": {
    "name": "agorararmard",
    "email": "aagouhar@efabless.com",
    "time": "Tue Jan 05 22:56:53 2021 +0200"
  },
  "message": "[DV] reduce power-up sequence time\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1a9c56256ad28c41443fa81d237e13267c019f53",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/mem_wb/mem_wb_tb.v",
      "new_id": "cfc82aacf93095e26c001623afe1823d61250e2c",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/mem_wb/mem_wb_tb.v"
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}