diff --git a/verilog/dv/wb_utests/mem_wb/Makefile b/verilog/dv/wb_utests/mem_wb/Makefile
index 60ea227..f7dcab3 100644
--- a/verilog/dv/wb_utests/mem_wb/Makefile
+++ b/verilog/dv/wb_utests/mem_wb/Makefile
@@ -23,7 +23,7 @@
 all:  ${PATTERN:=.vcd}
 
 %.vvp: %_tb.v
-	iverilog -I $(PDK_PATH) -I .. -I ../../../rtl \
+	iverilog -DFUNCTIONAL -I $(PDK_PATH) -I .. -I ../../../rtl \
 	$< -o $@
 
 %.vcd: %.vvp
diff --git a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
index 4784397..c604a33 100644
--- a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
+++ b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
@@ -18,7 +18,6 @@
 
 `timescale 1 ns / 1 ps
 
-`define FUNCTIONAL
 `define UNIT_DELAY #1
 
 `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"