)]}'
{
  "commit": "01e7303068f6c8810c4096e57d1e148bee71a6e9",
  "tree": "542c65665cf5544744d67b25aa4dce5598885f11",
  "parents": [
    "195158b0c071df817899f8ea8b24e4ef4c6b0e50"
  ],
  "author": {
    "name": "Anton Blanchard",
    "email": "anton@linux.ibm.com",
    "time": "Mon Feb 01 22:42:16 2021 +1100"
  },
  "committer": {
    "name": "Anton Blanchard",
    "email": "anton@ozlabs.org",
    "time": "Mon Feb 01 22:42:16 2021 +1100"
  },
  "message": "Add fake diode model for gate level simulation\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "478263bd75503efbafcf8d211125bac6dfa87777",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel_netlists.v",
      "new_id": "0bd58df5445bab3d64d2d02edd60096df672bca0",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel_netlists.v"
    }
  ]
}