commit ee11c5c54462185e9d68ef758432665752677a21
author DrAceX <dracex@hotmail.com> Wed Dec 16 12:36:57 2020 -0500
committer DrAceX <dracex@hotmail.com> Wed Dec 16 12:36:57 2020 -0500
tree da00b66530df2bdd8a430fe912a7bfa9df2665c0
parent 34d7e07fdde4e69633eaf9506af7fd25921ba048

Update README.md.

README.md

diff --git a/README.md b/README.md
index d7171e8..b68802e 100644
--- a/README.md
+++ b/README.md
@@ -82,19 +82,18 @@
 ### Verilog Module Hierarchy
 
 ```
-decred_top.v
+user_project_wrapper.v
    |
-    - clock_div.v
-   |
-    - decred.v
+    - decred_controller.v
+         |
+          - clock_div.v
          |
           - addressalyzer.v
          |
           - spi_*.v
          |
           - register_bank.v
-               |
-                - hash_macro_nonblock.v
+    - decred_hash_macro.v
 ```
 
 ## Building